Technology scaling of nanoelectronic circuits currently introduces a fundamental paradigm shift of architectures for high-performance computing. Due to power and noise issues, single chip architectures have to gain increased
performance by increased parallelism instead of increased frequency. Goal of this project is a methodology to map compute intensive portions of simulation algorithms to
configurable Network-on-Chip Multi-Processor System on a Chip (NoC MPSoCs).
Modern manufacturing processes are subject to high variations and a high
sensitivity during operation. This project addresses the need for
innovative embedded diagnosis solutions for such systems to reduce
time-to-market with reasonable costs.
In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.
Assuring a certain reliability level for mechatronic systems becomes more and
more important as human life is affected by it. For a careful estimation
of the system reliability not only the reliability of each individual
component has to be taken into account but also the interaction among the
components. In this project, tools and methodologies to improve
reliability on the electronic layer of such systems are developed.
The elevated power dissipation during test has severe impact on test time, test reliability and product reliability, especially for high-performance processors like the Cell Processor. In the course of this project, new methods for test planning that take advantage of clock gating and power gating are developed.
High-end digital circuits need a very large amount of test vectors.
Given such
high data volumes, test cost is predicted to explode by a factor of 120.
This project addresses this challenge by developing and integrating
innovative technology for generating and capturing data on-chip.
DFX is a logic synthesis tool and gate level simulator for circuit descriptions in VHDL and other hardware description languages. Besides that, DFX contains modern fault simulators and automatic test pattern generators for computer aided testing of integrated circuits.
This project tackles issues regarding power consumption during self-test of microprocessors. A new method is proposed which achieves high fault coverage, short test time with a small power/energy budget on the target system.
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