Prototyping Environment and Design Flow for ARM Based Systems

In this project we set up an environment that supports the development of embedded systems consisting of an ARM microprocessor running embedded software and application-specific hardware, both interacting via a common bus system. Further components such as memories and standard peripherals may be connected to the bus. The prototyping environment shall support the modelling and simulation of the system based on transaction level SystemC (covering the bus systems and all attached hardware excluding the ARM) and the ARM instruction set simulator "Armulator". Based on commercial EDA software and compilers, a design flow will be set up that allows to implement a prototype on a NEC SoClite+ prototyping board which includes an ARM7TDMI-S microprocessor core, an FGPA for application-specific logic, and several types of memory and peripheral components.

Simulation Hardware / Software Modelling and Interfacing for NoC MPSoC Computers

Configurable Network-on-Chip Multi-Processor Systems-on-a-Chip (NoC-MPSoCs) are an emerging architecture for simulation applications. In this project we study the interactions between simulation software and such hardware structures, providing a software interface that allows configuring the on-chip hardware resources, and enabling the development of a meta-model for a wide range of configurable NoC-MPSoCs. The model shall provide performance assessment even under the occurrence and handling of faults, and be suitable for simulation, thus forming a virtual prototype that enables the investigation of prospective NoC-MPSoC architectures for given simulation applications long before the hardware gets available. This eases the Hardware / Software Co-Design for simulation applications and allows to anticipate and estimate the impact of future hardware architectures on the simulation performance.

This research is part of Research Area F of the SimTech cluster.

Transaction-Level Modeling Methodologies and Simulation Mechanisms for State of the Art MPSoCs and Embedded Systems

By enabling very fast system-level simulations, transaction-level modeling (TLM) has become a very popular approach to design of embedded systems and Systems-on-Chip. TLM languages, methodologies and simulation environments have originally focused on traditional bus-based systems with static architectures and were based on the classical event-driven simulation mechanisms. Deficiencies of these early models when applied to advanced systems and architectures are being felt by academia and industry. Examples are systems with dynamic architectures (e.g. partially reconfigurable systems) and massively parallel architectures with complex network-like communication infrastructures. In this project we develop formalisms, modeling guidelines and mechanisms (e.g. adaptive models) to overcome the above mentioned deficiencies