Journals and Conferences

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Universität Stuttgart

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	Institut für Technische Informatik
	Journals and Conferences


		2008 Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin 2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), 29.09 - 01.10.2008, Ingolstadt, Germany Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen M. Kochte, R. Baranowski, H.-J. Wunderlich 2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), 29.09 - 01.10.2008, Ingolstadt, Germany Integrating Scan Design and Soft Error Correction M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin 14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008 Scan Chain Clustering for Test Power Reduction M. Elm, M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, J. Leenstra, N. Maeding 45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008 Selective Hardening in Early Design Steps C. G. Zoellin, H.-J. Wunderlich, I. Polian, B. Becker 13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008 A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer M. A. Kochte, R. Natarajan ACM International Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008 Signature Rollback - A Technique for Testing Robust Circuits U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich IEEE VTS'08 (26th VLSI Test Symposium), San Diego, California, USA, Apr 27th to May 1st, 2008 Scan Chain Organization for Embedded Diagnosis M. Elm, H.-J. Wunderlich Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, pp. 468-473 Test Set Stripping Limiting the Maximum Number of Specified Bits M. A. Kochte, C. G. Zoellin, M. E. Imhof, H.-J. Wunderlich 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008 Best paper award 2007 Academic Network for Microelectronic Test Education F.Novak, A.Biasizzo, Y.Bertrand, M-L.Flottes, L.Balado, J.Figueras, S.Di Carlo, P.Prinetto, N.Pricopi, H-J.Wunderlich and J-P.van der Hayden International Journal of Engineering Education, Volume 23 Number 6 2007, pp. 1245-1253 Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper) H.-J. Wunderlich, M. Elm, S. Holst 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 12-14, 2007, pp. 27-36 Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper) S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 12-14, 2007, pp. 3-10 A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction S. Hellebrand, C.G. Zoellin, H.-J. Wunderlich, T. Coym, S. Ludwig, B. Straube Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007, pp. 50-58 Programmable Deterministic Built-in Self-test A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 23 - 25, 2007 Scan Test Planning for Power Reduction M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra 44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007, pp. 521-526 Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair P. Öhler, S. Hellebrand, H.-J. Wunderlich 10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007, pp. 185-190 Best paper award An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy P. Öhler, S. Hellebrand, H.-J. Wunderlich 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 91-96 Adaptive Debug and Diagnosis without Fault Dictionaries S. Holst, H.-J. Wunderlich 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 7-12 Best paper award Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen M. Wedel, P. Göhner, J. Gäng, B. Bertsche, H.-J. Wunderlich, T. Arnaout In: 5. Paderborner Workshop "Entwurf mechatronischer Systeme", J. Gausemeier et al. (ed.), Bd. 210, Paderborn, Germany, March 22-23, 2007, pp. 257-272 Deterministic Logic BIST for Transition Fault Testing V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers IET Proceedings on "Computers & Digital Techniques" 1, (3), 2007, pp. 180-186 Test und Zuverlässigkeit nanoelektronischer Systeme B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp. 139-140 Synthesis of Irregular Combinational Functions with Large Don't Care Sets V. Gherman, H.-J. Wunderlich, R.D.- Mascarenas, J.Schloeffel, M. Garbers ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa - Lago Maggiore, Italy, March 11-13, 2007, pp. 287-292 Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp.69-76 2006 DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311 BIST Power Reduction Using Scan-Chain Disable in the Cell Processor C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 24 - 26, 2006, pp. 1-8 Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich Proc. of the IFIP International Conference on Very Large Scale Integration (VLSI-Soc), Nice, France, October 16 - 18, 2006, pp. 403-408 Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich Proc. of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006, pp. 359-364 Deterministic Logic BIST for Transition Fault Testing V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers Proc. of the European Test Symposium (ETS), Southampton, UK, May 22 - 25, 2006, pp. 123-128 X-Masking During Logic BIST and its Impact on Defect Coverage Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, M. Wittke IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 14, No. 2, February 2006, pp. 193-202 Software-Based Self-Test of Processors under Power Constraints J. Zhou, H.-J. Wunderlich Proc. of the 9th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 430 - 436, March 06 - 10, 2006 Some Common Aspects of Design Validation, Debug and Diagnosis T. Arnaout, G. Bartsch, H.-J. Wunderlich Proc. of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA), Kuala Lumpur, Malaysia, January 17-19, 2006, pp. 3-8 2005 On the Reliability Evaluation of SRAM-based FPGA Designs O. Héron, T. Arnaout, H.-J. Wunderlich Proc. of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24 - 26, 2005, pp. 403-408 Development of an Audio Player as System-on-a-Chip using an Open Source Platform P. Kiatisevi, L. Azuara, R. Dorsch, H.-J. Wunderlich Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23 - 26, 2005, pp. 2935-2938 From Embedded Test to Embedded Diagnosis H.-J. Wunderlich Proc. of the 10th IEEE European Test Symposium (ETS), Tallinn, Estonia, May 22 - 25, 2005, pp. 216-221 Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker Proc. of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp.11-18 Implementing a Scheme for External Deterministic Self-Test A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel Proc. of the 23rd IEEE VLSI Test Symposium (VTS), Palm Springs, CA, USA, May 1-5, 2005, pp. 101-106 Frühe Zuverlässigkeitsanalyse mechatronischer Systeme P. Jäger, B. Bertsche, T. Arnaout, H.-J. Wunderlich Proc. 22. VDI Tagung Technische Zuverlässigkeit, Stuttgart, Germany, April 7-8, 2005, pp. 39-56 2004 X-Masking During Logic BIST and its Impact on Defect Coverage Y.Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker, Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 442-451 Efficient Pattern Mapping for Deterministic Logic BIST V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 48-56 Reliability Considerations for Mechatronic Systems on the Basis of a State Model P. Göhner, E. Zimmer, T. Arnaout, H.-J. Wunderlich, Proc. of the 17th International Conference on Architecture of Computing Systems (ARCS) Augsburg, Germany, March 23-26, 2004, pp. 106-112 Impact of Test Point Insertion on Silicon Area and Timing during Layout H. Vranken, F. S. Sapei, H.-J. Wunderlich Proc. of the 7th Conference on Design, Automation and Test in Europe (DATE) Paris, France, February 16-20, 2004, pp. 810-815 2003 Test Engineering Education in Europe: the EuNICE-Test Project Y. Bertrand, M.-L. Flottes, L. Balado, J. Figueras, A. Biasizzo, F. Novak, S. Di Carlo, P. Prinetto, N. Pricopi, H.- J. Wunderlich Proc. of the IEEE International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 1-2, 2003, pp. 85-86 2002 Adapting a SoC to ATE Concurrent Test Capabilities M. Fischer, R. Huerta Rivera, R. Dorsch, H.-J. Wunderlich Proc. of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002, pp. 1169-1175 High Defect Coverage with Low Power Test Sequences in a BIST Environment P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, H.-J. Wunderlich IEEE Design and Test of Computers, Vol. 19, Issue 5, September/October 2002, pp. 44-52 Efficient On- and Off-Line Testing of Embedded DRAMs S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik IEEE Transaction on Computers, Vol. 51, No. 7, July 2002, pp. 801-809 Combining Deterministic Logic BIST with Test Point Insertion H. Vranken, F. Meister, H.-J. Wunderlich Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 389-394 RESPIN++ - Deterministic Embedded Test L. Schäfer, R. Dorsch, H.-J. Wunderlich Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 139-146 Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST H.-G. Liang, S. Hellebrand, H.-J. Wunderlich Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April 2002, pp. 157-168 On applying the set covering model to reseeding S. Chiusano and S. di Carlo and P. Prinetto and H. Wunderlich Proceedings of the conference on Design, automation and test in Europe (DATE01), 2001, pp. 156-161 Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability M. Kessler, G. Kiefer, J. Leenstra, K. Schünemann, T. Schwarz and H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 461-469 Tailoring ATPG for Embedded Testing R. Dorsch, H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 530-537 Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST H.-G. Liang, S. Hellebrand, H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 894-902 Reusing Scan Chains for Test Pattern Decompression R. Dorsch, H.-J. Wunderlich Proc. of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001, pp. 124-132 A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters S. Hellebrand, H-G Liang, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 17, No. 3/4, June/August 2001, pp. 341-349 A Modified Clock Scheme for a Low Power BIST Test Pattern Generator P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H.-J. Wunderlich Proc. of the 19th IEEE VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001, pp. 306-311 Circuit Partitioning for Efficient Logic BIST Synthesis A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001, pp. 86-91 2000 Minimized Power Consumption for Scan-Based BIST S. Gerstendörfer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 203-212 A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters S. Hellebrand, H-G Liang, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 778-784 Non-Intrusive BIST for Systems-on-a-Chip S. Chiusano, P. Prinetto, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 644-651 Application of Deterministic Logic BIST on Industrial Circuits G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 105-114 Optimal Hardware Pattern Generation for Functional BIST S. Cataldo, S. Chiusano, P. Prinetto, H.-J. Wunderlich Proc. of the 3rd Conference on Design, Automation and Test in Europe (DATE), Paris, France, March 27 - 30, 2000, pp. 292-297 Deterministic BIST with Partial Scan G. Kiefer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 169-177 1999 Minimized Power Consumption for Scan-Based BIST S. Gerstendörfer, H.-J. Wunderlich Proc. of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999, pp. 77-84 Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich Proc. of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999, pp. 339-350 Deterministic BIST with Partial Scan G. Kiefer, H.-J. Wunderlich Proc. of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999, pp. 110-117 Error Detecting Refreshment for Embedded DRAMs S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik Proc. of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, California, April 25-29, 1999, pp. 384-390 Symmetric Transparent BIST for RAMs V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich Proc. of the 2nd Conference on Design and Test in Europe (DATE), Munich, Germany, March 9-12, 1999, pp. 702-708 Deterministic BIST with Multiple Scan Chains G. Kiefer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Volume 14, No 1-2, February 1999, pp. 85-93 1998 Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST M. Karkala, N. A. Touba, H.-J. Wunderlich Proc. of the 7th Asian Test Symposium (ATS), Singapore, December 2-4, 1998, pp. 492-499 BIST for Systems-on-a-Chip H.-J. Wunderlich INTEGRATION - The VLSI Journal, December 1998, pp. 55-78 New Transparent RAM BIST Based on Self-Adjusting Output Data Compression V. N. Yarmolik, Y. Klimets, S. Hellebrand, H.-J. Wunderlich Proc. of Design & Diagnostics of Electronic Circuits & Systems (DDECS), Szczyrk, Poland, September 1998, pp. 27-33 Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications S. Hellebrand, H.-J. Wunderlich, A. Hertwig IEEE Design and Test, Vol. 15, No. 4, October-December 1998, pp. 36-41 Deterministic BIST with Multiple Scan Chains, G. Kiefer, H.-J. Wunderlich Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 1057-1064 Accumulator Based Deterministic BIST, R. Dorsch, H.-J. Wunderlich Proc. of the 29th IEEE International Test Conference (ITC), Washington, DC, October 1998, pp. 412-421 Hardware-Optimal Test Register Insertion A. P. Stroele, H.-J. Wunderlich IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, June 1998, pp. 531-540 Fast Self-Recovering Controllers A. Hertwig, S. Hellebrand, H.-J. Wunderlich Proc. of the 16th IEEE VLSI Test Symposium (VTS), Monterey, CA, April 1998, pp. 296-302 Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich Proc. of the 1st Conference on Design, Automation and Test in Europe (DATE), Paris, France, February 1998 pp. 173-179 Mixed-Mode BIST Using Embedded Processors S. Hellebrand, H.-J. Wunderlich, A. Hertwig Journal of Electronic Testing Theory and Applications (JETTA), Vol. 12, Nos. 1/2, February/April 1998, pp. 127-138 1997 Using BIST Control for Pattern Generation G. Kiefer, H.-J. Wunderlich Proc. of the 28th IEEE International Test Conference (ITC), Washington, DC, November 1997, pp. 347-355 STARBIST: Scan Autocorrelated Random Pattern Generation K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek Sadowska Proc. of the ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 1997, pp. 472-478 Fast Controllers for Data Dominated Applications A. Hertwig, H.-J. Wunderlich Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1997, pp. 84-89 1996 Bit-Flipping BIST H.-J. Wunderlich, G. Kiefer Proc. of the ACM/IEEE International Conference on CAD-96 (ICCAD), San Jose, CA, November 1996, pp. 337-343 Mixed-Mode BIST Using Embedded Processors S. Hellebrand, H.-J. Wunderlich, A. Hertwig Proc. of the 27th IEEE International Test Conference (ITC), Washington, DC, October 1996, pp. 195-204 Deterministic Pattern Generation for Weighted Random Pattern Testing B. Reeb, H.-J. Wunderlich Proc. of the European Design & Test Conference (ED&TC), Paris, France, March 1996, pp. 30-36 1995 Pattern Generation for a Deterministic BIST Scheme S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 88-94 Test Register Insertion with Minimum Hardware Cost A. P. Ströle, H.-J. Wunderlich Proc. of the ACM/IEEE International Conference on CAD-95 (ICCAD), San Jose, CA, November 1995, pp. 95-101 Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois IEEE Transactions on Computers, Vol. 44, No. 2, February 1995, pp. 223-233 Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors H.-J. Wunderlich, M. Herzog, J. Figueras, J.A. Carrasco, A. Calderon Proc. of the European Design & Test Conference (ED&TC), March 1995, pp. 573-580 1994 An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures S. Hellebrand, H.-J. Wunderlich Proc. of the ACM/IEEE International Conference on CAD-94 (ICCAD), San Jose, CA, November 1994, pp. 110-116 A Unified Method for Assembling Global Test Schedules A. Ströle, H.- J. Wunderlich Proc. of the 3rd Asian Test Symposium (ATS), Nara, Japan, November 1994, pp. 268-273 Simulation Results of an Efficient Defect Analysis Procedure O. Stern, H.-J. Wunderlich Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 729-738 Configuring Flip-Flops to BIST Registers A. Ströle, H.-J. Wunderlich Proc. of the 25th IEEE International Test Conference (ITC), Washington, DC, October 1994, pp. 939-948 Synthesis of Self-Testable Controllers S. Hellebrand, H.-J. Wunderlich Proc. of the European Design Automation Conference (EDAC/ETC/EuroAsic), Paris, France, March 1994, pp. 580-585 1993 An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick Proc. of the ACM/IEEE International Conference on CAD-93 (ICCAD), Santa Clara, CA, November 1993, pp. 572-577 1992 Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois Proc. of the 23rd IEEE International Test Conference (ITC), Baltimore, MD, September 1992, pp. 120-129 Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen O. Stern, H.-J. Wunderlich ITG-Fachbericht 119, 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, VDE-Verlag Stuttgart, March 1992, pp. 117-122 Efficient Test Set Evaluation H.-J. Wunderlich, M. Warnecke Proc. of the European Conference on Design Automation (EDAC), Brussels, March 1992, pp. 428-433 Prüfgerechter Entwurf und Test hochintegrierter Schaltungen H.-J. Wunderlich, M. H. Schulz Informatik-Spektrum, Vol. 15, Issue 1, February 1992, pp. 23-32 Optimized Synthesis Techniques for Testable Sequential Circuits B. Eschermann, H.-J. Wunderlich IEEE Transactions on Computer-Aided Design, Vol. 11, No.3, March 1992, pp. 301-312 The Pseudoexhaustive Test of Sequential Circuits H.-J. Wunderlich, S. Hellebrand IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No.1, January 1992, pp. 26-33 1991 Emulation of Scan Paths in Sequential Circuit Synthesis B. Eschermann, H.-J. Wunderlich Proc. of the 5th International Conference on Fault-Tolerant Computing Systems, Nürnberg, Springer-Verlag, Informatik Fachberichte, September 1991, pp. 136-147 A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic T. Kropf, H.-J. Wunderlich Proc. of the 22nd IEEE International Test Conference (ITC), Nashville, TE, October 1991, pp. 57-66 Signature Analysis and Test Scheduling for Self-Testable Circuits A. Ströle, H.-J. Wunderlich Proc. of the 21st International Symposium on Fault-Tolerant Computing (FTCS), Montreal, June 25-27, 1991, pp. 96-103 A Unified Approach for the Synthesis of Self-Testable Finite State Machines B. Eschermann, H.-J. Wunderlich Proc. of the 28th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1991, pp. 372-377 Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures H.-J. Wunderlich, A. Ströle Proc. of the International Symposium on Circuits and Systems (ISCAS), Singapur, June 11-14, 1991, pp. 1881-1884 TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control A. Ströle, H.-J. Wunderlich IEEE Journal of Solid-State Circuits, Vol.26, No.7, July 1991, pp. 1056-1063 Parallel Self-Test and the Synthesis of Control Units B. Eschermann, H.-J. Wunderlich Proc. of the 2nd European Test Conference (ETC), Munich, April 1991, pp. 73-82 1990 TEST CHIP: A Chip for Weighted Random Pattern Generation, Evaluation and Test Control A. Ströle, H.-J. Wunderlich, O.F. Haberl Proc. of the 16th European Solid-State Circuits Conference (ESSCC), Grenoble, France, 1990, pp. 101-104 Error Masking in Self-Testable Circuits A. Ströle, H.-J. Wunderlich Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 544-552 Generating Pseudo-Exhaustive Vectors for External Testing S. Hellebrand, H.-J. Wunderlich, O. F. Haberl Proc. of the 21st IEEE International Test Conference (ITC), Washington, DC, September 10-14, 1990, pp. 670-679 Methoden der Testvorbereitung zum IC-Entwurf H.-J. Wunderlich, M. H. Schulz Mikroelektronik, VDE-Verlag, Vol. 4, Issue 3, May/June 1990, pp. 112-115 Optimized Synthesis of Self-Testable Finite State Machines B. Eschermann, H.-J. Wunderlich Proc. of the 20th International Symposium on Fault-Tolerant Computing (FTCS), Newcastle, UK, June 26-28, 1990, pp. 390-397 The Effictiveness of Different Test Sets For PLAs P.C. Maxwell, H.-J. Wunderlich Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 628-632 Tools and Devices Supporting the Pseudo-Exhaustive Test S. Hellebrand, H.-J. Wunderlich Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, pp. 13-17 A Synthesis Approach to Reduce Test Overhead H.-J. Wunderlich, B. Eschermann Proc. of the 1st European Design Automation Conference (EDAC), Glasgow, UK, March 1990, p. 671 Multiple Distributions for Biased Random Test Patterns H.-J. Wunderlich IEEE Transactions on Computer-Aided Design, Vol. 9, No.6, June 1990, pp. 594-602 An Analytical Approach to the Partial Scan Problem H.-J. Wunderlich, A. Kunzmann Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 1, No. 2, 1990, pp. 163-174 1989 Methoden der Testvorbereitung H.-J. Wunderlich, M. H. Schulz Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 55-62 Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen F. Kesel, H.-J. Wunderlich Proc. of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, October 3-5, 1989, pp. 63-68 The Pseudo-Exhaustive Test of Sequential Circuits H.-J. Wunderlich, S. Hellebrand Proc. of the 20th IEEE International Test Conference (ITC), Washington, DC, 1989, pp. 19-27 The Design of Random-Testable Sequential Circuits H.-J. Wunderlich Proc. of the 19th International Symposium on Fault-Tolerant Computing (FTCS), Chicago, June 21-23, 1989, pp. 110-117 Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern H.-J. Wunderlich, F. Kesel GMD Berichte, 4. E.I.S.-Workshop, Bonn, February 1989, pp. 75-84 The Synthesis of Self-Test Control Logic O. Haberl, H.-J. Wunderlich Proc. of the COMPEURO 1989, Hamburg, May 8-12, 1989, pp. 5134-5136 1988 Automatisierung des Entwurfs vollständig testbarer Schaltungen S. Hellebrand, H.-J. Wunderlich Proc. GI - 18. Jahrestagung II, Hamburg, Informatik-Fachberichte 188, Springer-Verlag, 1988, pp. 145-159 Multiple Distributions for Biased Random Test Patterns H.-J. Wunderlich Proc. of the 19th IEEE International Test Conference (ITC), Washington, DC, September 12-14, 1988, pp. 236-244 Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits H.-J. Wunderlich, S. Hellebrand Proc. of the 18th International Symposium on Fault-Tolerant Computing (FTCS), Tokyo, Japan, June 27-30, 1988, pp. 36-45 Weighted Random Testing with Multiple Distributions Hans-Joachim Wunderlich Proc. of the 11th International Conference on Fault Tolerant Systems and Diagnostics , Akademie der Wissenschaften der DDR, Suhl, 1988, pp. 88-93 Integrated Tools for Automatic Design for Testability D. Schmid, H.-J. Wunderlich and F. Feldbusch, S. Hellebrand, J. Holzinger,A. Kunzmann Tool Integration and Design Environments, F. J. Rammig (Editor), Amsterdam: Elsevier Science Publishers B. V. (North Holland), IFIP, 1988, pp. 233-258 Output-maximal control policies for cascaded production-inventory systems with control and state constraints J. Warschat, H.-J. Wunderlich Int. Journal of Systems Sci., Vol. 19, No. 6, 1988, pp. 1011-1020 1987 The Random Pattern Testability of Programmable Logic Arrays H.-J. Wunderlich Proc. of the IEEE International Conference on Computer Design (ICCD), New York, 1987, pp. 682-685 On Computing Optimized Input Probabilities for Random Tests H.-J. Wunderlich Proc. of the 24th ACM/IEEE Design Automation Conference (DAC), Miami Beach, 1987, pp. 392-398 Self Test Using Unequiprobable Random Patterns H.-J. Wunderlich Proc. of the 17th International Symposium on Fault-Tolerant Computing (FTCS), Pittsburgh, 1987, pp. 258-263 1986 The Integration of Test and High Level Synthesis in a General Design Environment D. Schmid, R. Camposano, A. Kunzmann, W. Rosenstiel, H.-J. Wunderlich Proc. of the Integrated Circuits Technology Conference (ICTC), Limerick, Irland, 1986, pp. 317-331 On Fault Modeling for Dynamic MOS Circuits H.-J. Wunderlich, W. Rosenstiel Proc. of the 23rd ACM/IEEE Design Automation Conference (DAC), Las Vegas, 1986, pp. 540-546 1985 Design Automation of Random Testable Circuits A. Kunzmann, H.-J. Wunderlich Proc. of the European Solid-State Circuits Conference (ESSCIRC), Toulouse, 1985, pp. 277-285 PROTEST: A Tool for Probabilistic Testability Analysis H.-J. Wunderlich Proc. of the 22nd ACM/IEEE Design Automation Conference (DAC), Las Vegas, 1985, pp. 204-211 1984 Time-optimal control policies for cascaded production-inventory systems with control and state constraints J. Warschat, H.-J. Wunderlich Int. Journal of Systems Sci., Vol. 15, No. 5, 1984, pp. 513-524 Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin 2. GMM/ITG-Fachtagung „Zuverlässigkeit und Entwurf” (ZuE), 29.09 – 01.10.2008, Ingolstadt, Germany Abstract: Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen M. Kochte, R. Baranowski, H.-J. Wunderlich 2. GMM/ITG-Fachtagung „Zuverlässigkeit und Entwurf” (ZuE), 29.09 – 01.10.2008, Ingolstadt, Germany Abstract: Integrating Scan Design and Soft Error Correction M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin 14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008 Abstract: Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibility of the memory elements and further increases the need for protection. This paper presents a fault-tolerant register latch organization that is able t$ single-bit errors while it is clock gated. With active clock, single and multiple errors are detected. The registers can be efficiently integrated simil$ scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing. Scan Chain Clustering for Test Power Reduction Melanie Elm, Michael Imhof, Hans-Joachim Wunderlich, Christian Zoellin, Jens Leenstra, Nicolas Maeding 45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008 Abstract: An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits. Selective Hardening in Early Design Steps Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker 13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008 Abstract: Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer M. A. Kochte, R. Natarajan ACM International Conference on Computing Frontiers, Ischia, Italy, May 5-7, 2008 Abstract: We describe a software framework for deploying, scheduling and executing parallel DBMS user-defined programs on an attached high-performance computer (HPC) platform. This framework is advantageous for many DBMS workloads in the following two aspects. First, the long-running user-defined programs can be speeded up by taking advantage of the greater hardware parallelism available on the attached HPC platform. Second, the interactive response time of the remaining applications on the database server platform is improved by the off-loading of long-running user-defined programs to the attached HPC platform. Our framework provides a new approach for integrating high-performance computing into the workflow of query-oriented, computationally-intensive applications. Signature Rollback - A Technique for Testing Robust Circuits Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich IEEE VTS'08 (26th VLSI Test Symposium), San Diego, California, USA, Apr 27th to May 1st, 2008 Abstract: Scan Chain Organization for Embedded Diagnosis Melanie Elm, Hans-Joachim Wunderlich Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, pp. 468-473 Abstract: Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow. ftp pdf? Test Set Stripping Limiting the Maximum Number of Specifed Bits Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008 Abstract: This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets show a significant reduction in the maximum number of specified bits in the test patterns. Furthermore, results for commercial ATPG test sets show that even the overall number of specified bits is reduced substantially. ftp pdf? Academic Network for Microelectronic Test Education F.Novak, A.Biasizzo, Y.Bertrand, M-L.Flottes, L.Balado, J.Figueras, S.Di Carlo, P.Prinetto, N.Pricopi, H-J.Wunderlich and J-P.van der Hayden International Journal of Engineering Education, Volume 23 Number 6 2007, pp. 1245-1253 Abstract: This paper is an overview of the activities performed in the framework of the European IST project EuNICE-Test (European Network for Initial and Continuing Education in VLSI/SOC Testing) using remote automatic test equipment (ATE) ), addressing the shortage of skills in the microelectronics industry in the field of electronic testing. The project was based on the experience of the common test resource centre (CRTC) for French universities. In the framework of the EuNICE-Test project, the existing network expanded to 4 new academic centres: Universitat Politecnica de Catalunya, Spain, Politecnico di Torino, Italy, University of Stuttgart, Germany and Jozef Stefan Institute Ljubljana, Slovenia. Assessments of the results achieved are presented as well as course topics and possible future extensions. ftp pdf? Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper) H.-J. Wunderlich, M. Elm, S. Holst 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007 Abstract: Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level. ftp pdf? Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper) S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007 Abstract: The increased number of fabrication defects, spatial and temporal variability of parameters, as well as the growing impact of soft errors in nanoelectronic systems require a paradigm shift in design, verification and test. A robust design becomes mandatory to ensure dependable systems and acceptable yields. Design robustness, however, invalidates many traditional approaches for testing and implies enormous challenges. The RealTest Project addresses these problems for nanoscale CMOS and targets unified design and test strategies to support both a robust design and a coordinated quality assurance after manufacturing and during the lifetime of a system. The paper first gives a short overview of the research activities within the project and then focuses on a first result concerning soft errors in combinational logic. It will be shown that common electrical models for particle strikes in random logic have underestimated the effects on the system behavior. The refined model developed within the RealTest Project predicts about twice as many single events upsets (SEUs) caused by particle strikes as traditional models. ftp pdf? A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction S. Hellebrand, C.G. Zoellin, H.-J. Wunderlich, T. Coym, S. Ludwig, B. Straube Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007 Abstract: Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. In combinational logic a particle strike may lead to a glitch at the output of a gate, also referred to as single even transient (SET), which in turn can propagate to a register and cause a single event upset (SEU) there. Circuit level modeling and analysis of SETs provides an attractive compromise between computationally expensive simulations at device level and less accurate techniques at higher levels. At the circuit level particle strikes crossing a pn-junction are traditionally modeled with the help of a transient current source. However, the common models assume a constant voltage across the pn-junction, which may lead to inaccurate predictions concerning the shape of expected glitches. To overcome this problem, a refined circuit level model for strikes through pnjunctions is investigated and validated in this paper. The refined model yields significantly different results than common models. This has a considerable impact on SEU prediction, which is confirmed by extensive simulations at gate level. In most cases, the refined, more realistic, model reveals an almost doubled risk of a system failure after an SET. Programmable Deterministic Built-in Self-test A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 23 - 25, 2007 Abstract: In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministic patterns than existing programmable methods and provides high flexibility for test engineering in both internal and external test. Theoretical analysis suggests that significantly more care bits can be encoded in the seed of a Linear Feedback Shift Register (LFSR), if a limited number of conflicting equations is ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern. In contrast to known deterministic BIST schemes based on test set embedding, the embedding logic function is not hardwired. Instead, this information is stored in memory using a special compression and decompression method. Experiments for benchmark circuits and industrial designs demonstrate that the approach has considerably higher overall coding efficiency than the existing methods. Scan Test Planning for Power Reduction M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra 44th ACM/IEEE Design Automation Conference (DAC), San Diego, Ca, USA, June 4-8, 2007 Abstract: Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity. ftp pdf? (700 KB) Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair P. Öhler, S. Hellebrand, H.-J. Wunderlich 10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007 Abstract: An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). To advoid the prohibitive storage requirements for failure bitmaps and the complex data structures inherent in most algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either use very simple search strategies or restict the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to increased test times. Recently an integrated built-in test and repair approach has been proposed which interleaves test and repair analysis and supports an exact solution with moderate hardware overhead and reasonable test times. The search is based on a depth first traversal of a binary tree, which can be efficiently implemented using a stack of limited size. This algorithm can be realized with different repair strategies guiding the selection of spare rows or columns in each step. In this paper the impact of four different repair strategies on the test and repair time is analyzed. ftp pdf? (928 KB) An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy P. Öhler, S. Hellebrand, H.-J. Wunderlich 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007 Abstract: An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low. ftp pdf? (701 KB) Adaptive Debug and Diagnosis without Fault Dictionaries S. Holst, H.-J. Wunderlich 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007 Abstract: Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circiut, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. ftp pdf? (242 KB) Domänenübergreifende Zuverlässigkeitsbewertung in Frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen M. Wedel, P. Göhner, J. Gäng, B. Bertsche, H.-J. Wunderlich, T. Arnaout In: 5. Paderborner Workshop "Entwurf mechatronischer Systeme", J. Gausemeier et al.(ed.), Bd. 210, Paderborn, Germany, March 22-23, 2007, pp. 257-272 Abstract: Aufgrund der unvollständigen Informationen über ein mechatronisches System stellt die Frühe Zuverlässigkeitsbewertung eine gro ße Herausforderung dar. Um die jeweiligen Vorteile zu nutzen, wurden klassische Ansätze in den einzelnen Domänen kombiniert und in eine ganzheitliche Methode zur Zuverlässigkeitsbewertung in den Frühen Entwicklungsphasen integriert. In Zusammenarbeit verschiedener Ingenieursdisziplinen wurde die ganzheitliche Methode um die rechnergestützte Ermittlung von Fehlerzusammenhängen im Rahmen einer Risikoabschätzung und verschiedene qualitative Modellierungs- und Analyseansätze erweitert. für die systematische Analyse des wechselseitigen Einflusses der beteiligten Domänen und die Integration in die Zuverlässigkeitsbewertung wurden Wechselwirkungen zwischen den Domänen untersucht und klassifiziert. ftp pdf? (314 KB) Deterministic Logic BIST for Transition Fault Testing V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers IET Proceedings on "Computers & Digital Techniques" Abstract: BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification has been used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using difficult to test industrial designs. ftp pdf? (233 KB) Test und Zuverlässigkeit nanoelektronischer Systeme B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007, pp. 139-140 Abstract: Neben der zunehmenden Anfälligkeit gegenüber Fertigungsfehlern bereiten insbesondere vermehrte Parameterschwankungen, zeitabhängige Materialveränderung Störanfälligkeit während des Betriebs massive Probleme bei der Qualitätssicherung für nanoelektronische Systeme. Für eine wirtschaftliche Produktion und einen zuverlässigen Systembetrieb wird einerseits ein robuster Entwurf unabdingbar, andererseits ist damit auch ein Paradigmenwechsel beim Test erforderlich. Anstatt lediglich defektbehaftete Systeme zu erkennen und auszusortieren, muss der Test bestimmen, ob ein System trotz einer gewissen Menge von Fehlern funktionsfähig ist, und die verbleibende Robustheit gegenüber Störungen im Betrieb charakterisieren. Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine darauf abgestimmte Qualitätssicherung unterstützen. ftp pdf? (243 KB) Synthesis of Irregular Combinational Functions with Large Don't Care Sets V. Gherman, H.-J. Wunderlich, R.D.- Mascarenas, J.Schloeffel, M. Garbers ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa - Lago Maggiore, Italy, March 11-13, 2007, pp. 287-292 Abstract: A special logic synthesis problem is considered for Boolean functions which have large don't care sets and are irregular. Here, a function ist considered as orregular if the input assignments mapped to specified values ('1'or'0') are randomly spread over the definition space. Such functions can be encounted in the field of design for test. The proposed method uses ordered BDDs for logic manipulations and generates freeBDD-like covers. For the considered benchmark functions, implementations were found with the significant reduction of the node/gate count as compared to SIS or the methodes offered by a state-of-the-art BDD package. ftp pdf? (507 KB) Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute M.E. Imhof, C.G. Zöllin, H.-J. Wunderlich, N. Maeding, J. Leenstra Tagung Zuverlässigkeit und Entwurf (ZuD), Munich, Germany, March 26-28, 2007 Abstract: Die stark erhöhte durchschnittliche und maximale Verlustleistung während des Tests integrierter Schaltungen kann zu einer Beeinträchtigung der Ausbeute bei der Produktion sowie der Zuverlässigkeit im späteren Betrieb führen. Wir stellen eine Testplanung für Schaltungen mit parallelen Prüfpfaden vor, welche die Verlustleistung während des Tests reduziert. Die Testplanung wird auf ein Überdeckungsproblem abgebildet, das mit einem heuristischen Lösungsverfahren effizient auch für große Schaltungen gelöst werden kann. Die Effizienz des vorgestellten Verfahrens wird sowohl für die bekannten Benchmarkschaltungen als auch für große industrielle Schaltungen demonstriert. ftp pdf? (258 KB) DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich it - Information Technology, Vol. 48, No. 5, 2006, pp. 304-311 Abstract: Entwurf, Verifikation und Test zuverlässiger nanoelektronischer Systeme erfordern grundlegend neue Methoden und Ansätze. Ein robuster Entwurf wird unabdingbar um Fertigungsfehler, Parameterschwankungen, zeitabhängige Materialveränderungen und vorübergehende Störungen zu tolerieren. Gleichzeitig verlieren gerade dadurch viele traditionelle Testverfahren ihre Aussagekraft. Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine darauf abgestimmte Qualitätssicherung unterstützen. ftp pdf? (496 KB) (Zeitschrift: Information Technology) BIST Power Reduction Using Scan-Chain Disable in the Cell Processor C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 24 - 26, 2006, pp. 1-8 Abstract: Built-in self test is a major part of the manufacturing test procedure for the Cell Processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by standard low power design techniques. If special care is not taken, the scan-speed may have to be reduced significantly, thus extending test time and costs. In this paper, we describe a test power reduction method for logic BIST which uses test scheduling, planning and scan-gating. In LBIST, effective patterns that detect additional faults are very scarce after a few dozens of scan cycles and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern requires only a reduced set of the available scan chains to detect the fault and all don´t-care scan chains can be disabled, therefore significantly reducing test power. ftp pdf? (507 KB) Structural-based Power-aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich Proc. of the IFIP International Conference on Very Large Scale Integration (vlsi-soc), Nice, France, October 16 - 18, 2006, pp. 403-408 Abstract: Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as irdrop or ground bounce. Then, we propose a solution based on power-aware assignment of don´t care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS´89 and ITC´99 benchmark circuits with the proposed structural-based power-aware X-Filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length. ftp pdf? Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, H.-J. Wunderlich Proc. of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006, pp. 359-364 Abstract: Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don´t care bits in deterministic test patterns. For ISCAS´89 and ITC´99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution. ftp pdf? Deterministic Logic BIST for Transition Fault Testing V. Gherman, H.-J. Wunderlich, J. Schlöffel, M. Garbers Proc. of the European Test Symposium (ETS), Southampton, UK, May 22 - 25, 2006, pp. 123-128 Abstract: BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using industrial benchmark circuits. ftp pdf? (148 KB) X-Masking During Logic BIST and its Impact on Defect Coverage Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, M. Wittke IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 14, No. 2, February 2006, pp. 1-10 Abstract: We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area costs low, some known bits in output responses are also allowed to me masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n. ftp pdf? (817 KB) Software-Based Self-Test of Processors under Power Constraints J. Zhou, H.-J. Wunderlich Proc. of the 9th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 06 - 10, 2006, pp. 430-436 Abstract: Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initialization tests for the whole system. In this paper, for the first time a structural SBST methodology is proposed which optimizes energy, average power consumption, test length and fault coverage at the same time. ftp pdf? (258 KB) Some Common Aspects of Design Validation, Debug and Diagnosis T. Arnaout, G. Bartsch, H.-J. Wunderlich Proc. of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA), Kuala Lumpur, Malaysia, January 17-19, 2006, pp. 3-8 Abstract: Design, Verification and Test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping. ftp pdf? (232 KB) On the Reliability Evaluation of SRAM-based FPGA Designs O. Héron, T. Arnaout, H.-J. Wunderlich Proc. of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 403-408 Abstract: Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to soft errors, which are due to the high density of embedded SRAM cells. Reliability evaluation is an important step in designing highly reliable systems, which results in a strong competitive advantage in today's marketplace. This paper proposes a mathematical model able to evaluate and therefore help to improve the reliability of SRAM-based FPGAs. ftp pdf? (127 KB) Development of an Audio Player as System-on-a-Chip using an Open Source Platform P. Kiatisevi, L. Azuara, R. Dorsch, H.-J. Wunderlich Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23-26, 2005, pp. 2935-2938 Abstract: Open source software are becoming more widely-used, notably in the server and desktop applications. For embedded systems development, usage of open source software can also reduce development and licensing costs. We report on our experience in developing a Systemon- a-Chip (SoC) audio player using various open source components in both hardware and software parts as well as in the development process. The Ogg Vorbis audio decoder targeted for limited computing resource and low power consumption devices was developed on the free LEON SoC platform, which features SPARC-V8 architecture compatible processor and AMBA bus. The decoder runs on the open source RTEMS operating system making use of the royalty-free open source Vorbis library. We also aim to illustrate the use of hardware/software co-design techniques. Therefore, in order to speed up the decoding process, after an analysis, a computing-intensive part of the decoding algorithm was selected and designed as an AMBA compatible hardware core. The demonstration prototype was built on the XESS XSV-800 prototyping board using GNU/Linux workstations as development workstations. This project shows that development of SoC using open source platform is viable and might be the preferred choice in the future. ftp pdf? (131 KB) From Embedded Test to Embedded Diagnosis H.-J. Wunderlich Proc. of the 10th IEEE European Test Sypmposium (ETS), Tallinn, Estonia, May 22-25, 2005, pp. 216-221 Abstract: Testing integrated circuits with millions of transistors puts strong requirements on test volume, test application time, test speed, and test resolution. To overcome these challenges, it is widely accepted to partition test resources between the automatic test equipment (ATE) and the circuit under test (CUT). These strategies may reach from simple test data compression/decompression schemes to implementing a complete built-in self-test. Very often these schemes come with reduced diagnostic resolution. In this paper, an overview is given on techniques for embedding test into a circuit while still keeping diagnostic capabilities. Built-in diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping. ftp pdf? (215 KB) Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, B. Becker Proc. of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 11-18 Abstract: For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-target defect detection capabilities. For circuits with a large fraction of random-pattern resistant faults, the embedded deterministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-target defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects. ftp pdf? (91 KB) Implementing a Scheme for External Deterministic Self-Test A. W. Hakmi, V. Gherman, H.-J. Wunderlich, M. Garbers, J. Schlöffel Proc. of the 23rd IEEE VLSI Test Sypmposium (VTS), Palm Springs, CA, USA, May 1-5, 2005, pp. 101-106 Abstract: A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field. Keywords: Deterministic self-test, external BIST, test resource partitioning, test data compression. ftp pdf? (202 KB) Frühe Zuverlässigkeitsanalyse mechatronischer Systeme P. Jäger, B. Bertsche, T. Arnaout, H.-J. Wunderlich Proc. 22. VDI Tagung Technische Zuverlässigkeit, Stuttgart, April 7-8, 2005, pp. 39-56 Abstract: Mechatronische Systeme sind heutzutage allgegenwärtig. Durch die Kombination aus Mechanik und moderner Informationsverarbeitung (Elektronik und Software) kann die Leistungsfähigkeit von Produkten deutlich gesteigert werden. Ein Beispiel hierfür sind CVTGetriebe. Die ersten Getriebe dieser Bauart waren weitgehend mechanisch/hydraulische Strukturen [1]. Modernere CVT-Getriebe, wie das ZF Ecotronic [2] oder das Front-CVT der Mercedes-Benz A-Klasse [3] verfügen über eine elektronische Steuerung, die die Leistungsfähigkeit des Getriebes zu steigern vermag aber auch zu UnZuverlässigkeiten führen kann. In diesem Beitrag soll das Thema der Zuverlässigkeit mechatronischer Systeme aufgegriffen werden und insbesondere vor dem Hintergrund der Zuverlässigkeitsarbeit in Frühen Entwicklungsphasen diskutiert werden, da namentlich die Konzeptphase durch die Auswahl des richtigen Konzeptes für den endgültigen Produkterfolg hauptverantwortlich ist. Hierzu wird speziell das Thema der Informationsgewinnung in Frühen Phasen thematisiert, da der Erfolg der Zuverlässigkeitsarbeit maßgeblich von der Daten- und Informationslage abhängig ist. ftp pdf? (240 KB) X-Masking During Logic BIST and Its Impact on Defect Coverage Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, B. Becker Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 442-451 Abstract: We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n. Keywords: X-Masking, Logic BIST, Defect Coverage,Resistive Bridging Faults ftp pdf? (150 KB) Efficient Pattern Mapping For Deterministic Logic BIST V. Gherman, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, M. Garbers Proc. of the 35th IEEE International Test Conference (ITC), Charlotte, NC, USA, October 25-28, 2004, pp. 48-56 Abstract: Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates. Keywords: Logic BIST, BDDs ftp pdf? (146 KB) Reliability Considerations for Mechatronic Systems on the Basis of a State Model P. Göhner, E. Zimmer, T. Arnaout, H.-J. Wunderlich Proc. of the 17th International Conference on Architecture of Computing Systems (ARCS), Augsburg, Germany, March 23-26, 2004, pp. 106-112 Abstract: The first step in analyzing a problem is to establish a valid model that would represent this problem. The model helps mainly in understanding the problem by depicting it in a visual form. Hence, in order to analyze the reliability of mechatronic systems, we need to understand first how such systems fail and how they behave in the presence of a failure. This understanding would help us later in the analysis and the development of formal solutions to achieve the demanded reliability. This could be achieved using the model that we have developed, which will be presented in this paper. ftp pdf? (50 KB) Impact of Test Point Insertion on Silicon Area and Timing during Layout H.Vranken, F. S. Sapei, H.-J. Wunderlich Proc. of the 7th Conference on Design, Automation and Test in Europe (DATE), Paris, France, February 16-20, 2004, pp. 810-815 Abstract: This paper presents an experimental investigation on the impact of test point insertion on circuit size and performance. Often test points are inserted into a circuit in order to improve the circuit's testability, which results in smaller test data volume, shorter test time, and higher fault coverage. Inserting test points however requires additional silicon area and influences the timing of a circuit. The paper shows how placement and routing is affected by test point insertion during layout generation. Experimental data for industrial circuits show that inserting 1% test points in general increases the silicon area after layout by less than 0.5% while the performance of the circuit may be reduced by 5% or more. ftp pdf? (157 KB) Test Engineering Education in Europe: the EuNICE-Test Project Y. Bertrand, M.-L. Flottes, L. Balado, J. Figueras, A. Biasizzo, F. Novak, S. Di Carlo, P. Prinetto, N. Pricopi,H.-J. Wunderlich Proc. of the IEEE International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 1-2, 2003, pp. 85-86 Abstract: The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs for multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Micro-électronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC. ftp pdf? (140 KB) Adapting a SoC to ATE Concurrent Test Capabilities M. Fischer, R. Huerta Rivera, R. Dorsch, H.-J. Wunderlich Proc. of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002, pp. 1169-1175 Abstract: Concurrent test features are available in the next generation SoC testers to increase ATE throughput. To exploit these new features design modifications are necessary. In a case study, these modifications were applied to the open source Leon SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of Leon was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow for concurrent test are discussed. ftp pdf? (524 KB) High Defect Coverage with Low Power Test Sequences in a BIST Environment Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, H.-J. Wunderlich IEEE Design and Test of Computers, Vol. 19, Issue 5, September/October 2002, pp. 44-52 Abstract: A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact. ftp pdf? (185 KB) Efficient On- and Off-Line Testing of Embedded DRAMs S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik IEEE Transaction on Computers, Vol. 51, No. 7, July 2002, pp. 801-809 Abstract: This paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data. ftp pdf? (662 KB) Combining Deterministic Logic BIST with Test Point Insertion H. Vranken, F. Meister, H.-J. Wunderlich Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 389-394 Abstract: This paper presents a logic BIST approach which combines deterministic logic BIST with test point insertion. Test points are inserted to obtain a first testability improvement, and next a deterministic pattern generator is added to increase the fault efficiency up to 100%. The silicon cell area for the combined approach is smaller than for approaches that apply a deterministic pattern generator or test points only. The combined approach also removes the classical limitations and drawbacks of test point insertion, such as failing to achieve complete fault coverage and a complicated design flow. The benefits of the combined approach are demonstrated in experimental results on a large number of ISCAS and industrial circuits. ftp pdf? (128 KB) RESPIN++ - Deterministic Embedded Test L. Schäfer, R. Dorsch, H.-J. Wunderlich Proc. of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002, pp. 139-146 Abstract: RESPIN++ is a deterministic embedded test method tailored to system chips, which implement scan test at core level. The scan chains of one core of the system-on-a-chip are reused to decompress the patterns for another core. To implement the RESPIN++ test architecture only a few gates need to be added to the test wrapper. This will not affect the critical paths of the system. The RESPIN++ method reduces both test data volume and test application time up to one order of magnitude per core compared to storing compacted test patterns on the ATE. If several cores may be tested concurrently, test data volume and test application time for the complete system test may be reduced even further. This paper presents the RESPIN++ test architecture and a compression algorithm for the architecture. ftp pdf? (87 KB) Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST H.-G. Liang, S. Hellebrand, H.-J. Wunderlich Journal of Electronic Testing - Theory and Applications (JETTA), Vol. 18, No. 2, April, 2002, pp. 157-168 Abstract: In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and hoizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan esign, simple and flexible, so that sharing between several logic cores is p0ossible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility. ftp pdf? (152 KB) On applying the set covering model to reseeding S. Chiusano and S. di Carlo and P. Prinetto and H. Wunderlich Proceedings of the conference on Design, automation and test in Europe (DATE01), 2001, pp. 156-161 Abstract: The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the trade- off between area overhead and global test length as well as to deal with larger circuits. ftp pdf? (79 KB) Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability M. Kessler, G. Kiefer, J. Leenstra, K. Schünemann, T. Schwarz and H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 461-469 Abstract: In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scan-based BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines the delay fault testing characteristics at the macro boundaries. This specification is used to analyse and improve the delay fault testability by improving the scan chain ordering at macro-level before the macros are connected together into the total chip network. The hierarchical methodology has been evaluated with the instruction window buffer core of an out-of-order processor. It was shown that for this design practically no extra hardware is required. ftp pdf? (168 KB) Tailoring ATPG for Embedded Testing R. Dorsch, H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 530-537 Abstract: An automatic test pattern generation (ATPG) method is presented Testability for a scan-based test architecture which min-imizes ATE storage requirements and reduces the bandwidth be-tween the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test ar-chitecture and the tailored test patterns reduces the test data vol-ume up to two orders of magnitude compared with standard com-pacted test sets. ftp pdf? (117 KB) Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST H.-G. Liang, S. Hellebrand, H.-J. Wunderlich Proc. of the 32nd IEEE International Test Conference (ITC), Baltimore, MD, October 30-November 1, 2001, pp. 894-902 Abstract: In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and hoizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan esign, simple and flexible, so that sharing between several logic cores is p0ossible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility. ftp pdf? (152 KB) Reusing Scan Chains for Test Pattern Decompression R. Dorsch, H.-J. Wunderlich Proc. of the 6th European Test Workshop (ETW), Stockholm, Sweden, May 29-June 1, 2001, pp. 124-132 Abstract: The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly. ftp pdf? (126 KB) A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters S. Hellebrand, H-G Liang, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 17, No. 3/4, June/August 2001, pp. 341-349 Abstract: In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical techniques for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST.. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters. ftp pdf? (57 KB) A Modified Clock Scheme for a Low Power BIST Test Pattern Generator P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H.-J. Wunderlich Proc. of the 19th VLSI Test Symposium (VTS), Marina Del Rey, CA, April 29-May 3, 2001, pp. 306-311 Abstract: In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roughly the same as those achieved using a standard BIST scheme. The area overhead is nearly negligible and there is no penalty on the circuit delay. The proposed BIST scheme does not require any circuit design modification beyond the parallel BIST technique, is easily implemented and has low impact on the design time. It has been implemented based on an LFSR-based TPG, but can also be designed using a cellular automata. Reductions of the energy, average power and peak power consumption during test operation are up to 94%, 55% and 48% respectively for ISCAS and MCNC benchmark circuits. ftp pdf? (126 KB) Circuit Partitioning for Efficient Logic BIST Synthesis A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich Proc. of the 4th Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 12-16, 2001, pp. 86-91 Abstract: A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does not require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware. ftp pdf? (255 KB) Minimized Power Consumption for Scan-Based BIST S. Gerstendörfer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 203-212 Abstract: Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance. ftp pdf? (72 KB) A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters S. Hellebrand, H-G Liang, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 778-784 Abstract: In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical techniques for test width compression and with pseudo-random pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST.. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters. ftp pdf? (57 KB) Non-Intrusive BIST for Systems-on-a-Chip S. Chiusano, P. Prinetto, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 644-651 Abstract: The term functional BIST describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within other parts of the system. It is a promising solution for self-testing complex digital systems at reduced costs in terms of area overhead and performance degradation. While previous work mainly investigated the use of functional modules for generating pseudo-random and pseudo-exhaustive test patterns, the present paper shows that a variety of modules can also be used as a deterministic test pattern generator via an appropriate reseeding strategy. This method enables a BIST technique that does not introduce additional hardware like test points and test registers into combinational and pipelined modules under test. The experimental results prove that the reseeding method works for accumulator based structures, multipliers, or encryption modules as efficiently as for the classic linear feedback shift registers, and some times even better. ftp pdf? (104 KB) Application of Deterministic Logic BIST on Industrial Circuits G. Kiefer, H. Vranken, E. J. Marinissen, H.-J. Wunderlich Proc. of the 31st IEEE International Test Conference (ITC), Atlantic City, NJ, October 3-5, 2000, pp. 105-114 Abstract: We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized. ftp pdf? (119 KB) Optimal Hardware Pattern Generation for Functional BIST S. Cataldo, S. Chiusano, P. Prinetto, H.-J. Wunderlich Proc. of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000, pp. 292-297 Abstract: Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as hardware test pattern generator. Up to now, only linear feedback shift registers and accumulator based structures have been used for deterministic test pattern generation by reseeding. In this paper, a method is proposed which can be applied to general finite state machines. Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module. Experiments prove the effectiveness of the approach which outperforms previous results for accumulators, in terms of test size and test time, without sacrifying the fault detection capability. ftp pdf? (89 KB) Deterministic BIST with Partial Scan G. Kiefer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 16, No. 3, June 2000, pp. 169-177 Abstract: An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead. ftp pdf? (133 KB) Minimized Power Consumption for Scan-Based BIST S. Gerstendörfer, H.-J. Wunderlich Proc. of the 30th IEEE International Test Conference (ITC), Atlantic City, NJ, September 28-30, 1999, pp. 77-84 Abstract: Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance. ftp pdf? (72 KB) Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich Proc. of the 3rd European Dependable Computing Conference (EDCC), Prague, Czech Republic, September 15-17, 1999, pp. 339-350 Abstract: The paper presents a new approach to transparent BIST for word-oriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST scheme are comparable to the conventional transparent BIST structures. Experimental results show that in many cases the proposed test techniques achieve a higher fault coverage in shorter test time. ftp pdf? (126 KB) Deterministic BIST with Partial Scan G. Kiefer, H.-J. Wunderlich Proc. of the 4th IEEE European Test Workshop (ETW), Constance, May 25-28, 1999 , pp. 110-117 Abstract: An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead. ftp pdf? (133 KB) Error Detecting Refreshment for Embedded DRAMs S. Hellebrand, H.-J. Wunderlich, A. Ivaniuk, Y. Klimets, V. N. Yarmolik Proc. of the 17th IEEE VLSI Test Symposium (VTS), Dana Point, CA, April 25-29, 1999, pp. 384-390 Abstract: This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the refresh cycle for concurrently computing a test characteristic of the memory contents and compare it to a precomputed reference characteristic. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). It also achieves a very high error coverage at low hardware costs. Therefore it perfectly complements standard on-line checking approaches relying on error detecting codes, where the detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data. ftp pdf? (58 KB) Symmetric Transparent BIST for RAMs V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich Proc. of the 2nd Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 9-12, 1999, pp. 702-708 Abstract: The paper introduces the new concept of symmetric transparent BIST for RAMs. This concept allows to skip the signature prediction phase of conventional transparent BIST approaches and therefore yields a significant reduction of test time. The hardware cost and the fault coverage of the new scheme remain comparable to that of a traditional transparent BIST scheme. In many cases, experimental studies even show a higher fault coverage obtained in shorter test time. ftp pdf? (59 KB) Deterministic BIST with Multiple Scan Chains G. Kiefer, H.-J. Wunderlich Journal of Electronic Testing: Theory and Applications (JETTA), Volume 14, Numbers 1-2, February 1999, pp. 85-93 Abstract: A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage i