Software infrastructure for CAD support of complex test architectures

Many different architectures for Design For Test (DFT) have been proposed over the years, such as scan chains, DFT for Built-In Self Test or DFT incorporating test data compression. Because of the variety of different approaches, it is until now rather cumbersome to adapt the existing CAD tools for Electronic Design Automation (EDA) to new DFT. Most of the time, the circuit is manually converted into a strictly combinatorial representation of the original circuit-under-test.

In order to more easily support new DFT architectures, a software infrastracture should be designed, that combines the existing algorithms and tools implemented in the Signs Framework with logic simulation and circuit transformation. For example, most BIST architectures contain some form of Pattern Generator and Signature Register. These components can be stripped from the circuit under test and can be used to generate test patterns using the existing logic simulator.

The goals of the thesis are:

• Circuit partitioning into parts used for pattern generation and signature, and the parts under test
• Computing the combinatorial representation of the partition being tested
• Evaluating the software infrastructure with existing DFT architectures
• Optionally applying the infrastracture to large industrial designs with support for different clocking strategies and partial scan

Contact: Christian Zöllin ( Email: christian.zoellin@informatik.uni-stuttgart.de )