Deriving sequential error propagation probabilities from circuit descriptions
Transient faults, faults caused by temporary disturbance of the circuit, are
considered to be a major problem in future circuit designs that build upon
nanoelectronic technology. Once a transient fault has occured inside the
sequential element (such as a Flip-Flop) of a circuit, it can either be
canceled out because the current state of the circuit does not create an active
path to another memory elements, or it is propagated into other sequential
elements eventually leading to an faulty system output.
The probability of a transient fault being propagated to a system output is
highly dependent on the topology and state of the circuit and accurate
computation of the probabilities is not feasible except for the smallest of
circuits. Statistical methods have proven to be more promising in order to
estimate error propagation probabilities for large circuit and can be used to
find hot-spots with high likelihood for causing erroneous system outputs and
will consequently be used to focus error correction effort.
The goals of the thesis are:
Conducting a survey of existing proposals for computing error propagation
probabilities and evaluating these methods regarding their feasibility for
large industrial circuits
Implementing a method from the survey and conducting a study, that compares
error probabilities under the assumption, that the error propagation
probabilities can be changed by some form of error correction