Aggressive scaling of device structures increased the susceptibility of
hardware
designs to transient faults and ageing effects, making reliability
estimation
of a design a required step in the design flow. Reliability can be assessed
empirically by fault injection into the design under investigation
followed by
simulation or emulation.
This thesis targets a fault injection framework for hardware designs
that allows to
inject different types of faults into the components of the
design and evaluate their impact during
runtime. Requirements on this framework are
Efficient evaluation of a large number of different faults,
including permanent and transient faults
Evaluation of output response of the circuit.
The framework shall be demonstrated on a design of moderate complexity, for
instance a JPEG compressor.