Graphpartitioning in VLSI Design

K-way Partitioning of Graphs and Hypergraphs is a common application in VLSI Design. It is used in circuit partitioning for emulation- and rapid-prototyping platforms as well as in Design-for-Testability and Design-for-Low-Power. In the scope of this Master Thesis different partitioning algorithms shall be analyzed and compared systematically. In a second step existing partitioning tools shall be integrated into the department's tool chain and afterwards exemplarily applicated to a recent problem in the VLSI design. The problem can be chosen from the fields of Low-Power-Testing or Design-for-Diagnosis. Big industrial circuits will be available for the final evaluation of the tools' performance.

Contact:
Prof. Dr. Hans-Joachim Wunderlich ( Email: wu@informatik.uni-stuttgart.de )
Melanie Elm ( Email: Melanie.Elm@iti.uni-stuttgart.de )