Area-Efficient Time Compaction of Diagnostic Circuit Responses for Multicore Architectures

The recent development in FPGA, Network-on-Chip and Multi- and Manycore architectures takes advantage of the intrinsic reconfigurability of such systems. Lifetime, reliability and also yield is improved by reconfiguration upon failure. To enable the use of repair mechanisms it is indispensable to first locate (diagnose) the failing device and the reason for its failure.

Diagnosis requires to gather a large amount of data produced by testsets for different types of faults and subsequent analysis. Especially in online repair environments it is impossible to store or to transfer this large amount of data among the cores. Therefore it is necessary to equip each core with dedicated hardware structures which enable the identification of valuable information for diagnosis in this large amount of data and compress it into as few as possible bits.

In this thesis a time compaction scheme for test responses, which stores only valuable data for diagnosis, has to be developed and implemented. The time compaction has to be applied subsequent to a space compaction with a simple parity tree [2], [3]. This space compaction has been proven to preserve enough diagnostic information for a proper diagnosis of faulty behavior with for instance the POINTER [4] diagnosis method.

The time compaction can be based on a modulo-2 address characteristic [5]. The responses of the space compactor can be viewed as a sequence of words with a width of t bits, where t is the length of the longest scan path. The POINTER diagnosis approach has to be adapted to perform diagnosis on a timecompacted word (signature). The signature comparison has to be implemented on-chip.

The positions of corrupted signatures can additionally be stored, respectively compacted as a modulo-2 address characteristic. To determine the testvectors with corrupted signatures, check points have to be inserted at proper places into the test sequence. A backtracking scheme to retrieve the failing test vectors between two check points has to be implemented.

The thesis can be written in English or German.

List of useful literature:
[1] M.L. Bushnell, V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers (2000)
[2] Vranken, H., Goel, S. K., Glowatz, A., Schloeffel, J., and Hapke, F. 2006. Fault detection and diagnosis with parity trees for space compaction of test responses. In Proceedings of the 43rd Annual Conference on Design Automation (San Francisco, CA, USA, July 24 - 28, 2006). DAC '06. ACM, New York, NY, 1095-1098.
[3] Melanie Elm, Hans-Joachim Wunderlich. Scan Chain Organization for Embedded Diagnosis. Design, Automation and Test in Europe (DATE'08), Munich, Germany, March 10-14, 2008, pp. 468-473.
[4] S. Holst, H.-J. Wunderlich. Adaptive Debug and Diagnosis without Fault Dictionaries. 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007, pp. 7-12.
[5] V. N. Yarmolik, Y. Klimets, S. Hellebrand, H.-J. Wunderlich. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Proc. of Design & Diagnostics of Electronic Circuits & Systems (DDECS), Szczyrk, Poland, September 1998, pp. 27-33.

Contact:
Prof. Dr. Hans-Joachim Wunderlich ( Email: wu@informatik.uni-stuttgart.de )
Melanie Elm ( Email: Melanie.Elm@iti.uni-stuttgart.de )