1. Parallelized Simulation of Temporally Decoupled Transaction Level Models on Multi-Core Simulation Hosts

The increasing complexity of the systems being modeled and simulated in SystemC has motivated researchers to work on parallel and distributed alternatives for the sequential SystemC kernels. This research direction is further justified by the increasing availability of multi-core CPUs which bring the power of parallel computing to ordinary personal computers and development workstations. In contrast to general, “free-form” SystemC models, transaction level models (TLMs) follow certain modeling guidelines and use certain forms of inter-process communication which make them more suitable for parallelization. “Temporally decoupled” models as proposed by the OSCI TLM 2.0 standard are an excellent example. The objective of this thesis is to devise and implement a mechanism for parallelized simulation of temporally decoupled transaction level models on shared memory multi-core simulation hosts. By exploiting the architectural properties of multi-core CPUs, it should be possible to avoid overheads present in the more general distributed approaches. For more information please contact Rauf Salimi Khaligh .

2. Accuracy-Adaptive Transaction Level Simulation of Hardware-Software Systems

An ongoing research of our group is the development of accuracy-adaptive transaction level simulation concepts, tools and models. In contrast to traditional transaction level models where the abstraction level is fixed, adaptive models change their abstraction levels dynamically to achieve a better simulation performance without losing the required level of accuracy. The objective of this thesis is extension of our current approach to systems with software processing elements, and integration of instruction set simulators (ISSs) in an accuracy-adaptive simulation context. For more information please contact Rauf Salimi Khaligh .