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Completed Master Thesis
SS 2008
- Adán Kohler
Modellierung und Simulation von Networks-on-Chip auf der Transaktionsebene
Networks-on-Chip (NoC) dienen der Kommunikation zwischen Prozessorelementen
von Multiprozessor-Systems-on-Chip (MPSoC). Beim Entwurf von NoCs müssen
Netzwerktopologien, Routingmechanismen und weitere Aspekte des Netzwerks so
ausgewählt werden, dass die Kommunikationsanforderungen zu implementierender
Anwendungen erfüllbar sind. Um dies bewerten zu können, ist eine Simulation
des Netzwerks unter Einbeziehung des Kommunikationsverhaltens der
Prozessorelemente erforderlich.
Für busbasierte Systeme wurde die Transaktionsebenen-Modellierung und
–Simulation entwickelt, welches Kommunikationsoperationen zu sogenannten
Transaktionen zusammenfasst und durch Abstraktion von Protokolldetails (z.B.
einzelne Signale) eine höhere Simulationsperformance erzielt. In dieser
Diplomarbeit soll das Transaktionskonzept nun zur Modellierung von NoCs
angewandt und, falls erforderlich, angepasst werden. Dabei kann auf die
Simulationsbibliothek SystemC sowie die TLM2.0-Bibliothek für die
Transaktionsebenensimulation aufgesetzt werden. Es soll ein geeigneter
Rahmen, etwa in Form einer NoC-Simulationsbibliothek mit definierten
Interfaces, geschaffen werden, der es den Anwendern erlaubt, die Details
einer NoC-Architektur (Topologie, Routing etc.) selbst zu definieren.
WS 2007/08
- George Raju
Transaction Level Modelling of H.264 Decoding Processes
The standard H.264 / MPEG-4 part 10 defines an encoded representation of
digital video sequences and its decoding process. The decoding process is
implemented as software in the JM reference model. Due to its sequential
nature, the JM reference is not well-suited as a reference against which a
parallel hardware implementation of a H.264 decoder could be verified. The
subject of this thesis is the design of a parallel reference model of H.264
decoding in SystemC. The model shall be designed at the Transaction Level of
abstraction.
SS 2007
- Ms. Weining Hao
Architecture and Implementation of a H.264 Deblocking Accelerator
The standard H.264 / MPEG-4 part 10 defines an encoded representation of
digital video sequences and its decoding process.
This process includes a deblocking sub-process to reduce the visual impact of
block artefacts. Different to previous video coding standards, H.264
deblocking is part of the decoding loop (“in-loop filter”). The
de-blocked video frames serve as a reference for the decoding of other frames
that are decoded later.
Therefore, the deblocking process is time-critical. Furthermore, deblocking
is known to contribute about one third to the performance requirements of
H.264 decoding. The subject of this thesis is the design of a hardware
accelerator for H.264 deblocking that can speed up the execution of an
otherwise software-based decoder.
- Thomas Bruni
A Formalized Approach to Transaction Level Modeling
In transaction level modeling (TLM), high simulation speed is achieved by
modeling at higher levels of abstraction than signals and the RTL.
The level of abstraction in which modeling is performed depends on the
context in which a model is used and the required level of accuracy.
The levels of accuracy required in most modeling activities have been
identified and proposed by some researchers and institutes active in the TLM
field.
For example, the OSCI TLM approach proposes PV (Programmer's View), PVT
(Programmer's View with Timing), CX (Cycle Approximate) and CA (Cycle
Accurate) abstraction levels, in increasing order of precision and decreasing
order of simulation speed. However, these definitions of the abstraction
levels are informal and the transition from one abstraction level to another
is not systematic or automatizable. For example, although transaction level
models of a bus at different abstraction levels represent the same underlying
communication protocol, the CX, CA and PVT models are often developed
independently with little or no reuse. The objective of this Thesis is
development of a more formal, generic modeling approach for modeling of
buses, so that based on a single formal description (e.g. communicating state
machines), models at different abstraction levels can be generated in a
systematic and potentially automatizable manner. The proposed approach shall
be validated using an existing bus protocol, and the final executable models
shall be implemented in SystemC.
- Muhammad Shaharyar Awan
Transaction Level Power and Timing Exploration of Bus Architectures
In modern embedded systems, low power consumption is an increasingly
important factor that should be taken into account when exploring the design
space.
Limited energy resources such as batteries, size constraints and limited
cooling possibilities have motivated power aware design techniques, which in
addition to performance and timing, take the power consumption limitations
into account.
Low power design at lower levels (i.e. physical, gate and transistor levels)
has been extensively studied and successfully applied to complex integrated
circuits such as microprocessors. A recent trend is system-level power aware
design, in which power consumption is analyzed and optimized at higher
levels.
For example, software optimization techniques which reduce cache misses and
hence result in fewer external memory accesses and lower power consumption.
Another example is power consumption of buses, where factors such as the
number of transitions on the address, data and control lines directly affect
the power consumption.
Therefore, factors such as arbitration policies and address/data coding
schemes can be used to control the power consumption associated with a bus.
The objective of this thesis is conception and development of an OSCI-TLM
based framework for unified power and timing exploration. The focus is on the
bus model and the effect of different arbitration policies on timing and
power consumption. A model of an existing bus protocol shall be developed.
For masters and slaves, generic models with simple power models (e.g. simple
traffic pattern generators for masters and memory modules for slaves) shall
be implemented and used in the experiments.
- Adán Kohler
Studienarbeit
Portierung und Optimierung einer H.264-Dekodier-Software für ein eingebettetes System
Der Standard H.264 / MPEG-4 Part 10 definiert eine kodierte Repräsentation
für digitalisierte Videosequenzen und einen dazugehörigen Dekodierprozess für
verschiedene Bildauflösungen (Levels) und mit verschiedenen Kombinationen
alternativer Kodierverfahren (Profiles). Der Dekodierprozess ist (mit
Einschränkungen bezüglich Profiles und Levels) durch die Open Source Software
X264 implementiert. Aufgabe dieser Studienarbeit ist es, diese für
Desktop-Rechner geschriebene Software auf ein Embedded Development Board (ARM
Versatile Platform Board mit ARM926EJ-S Prozessor) zu portieren. Ferner soll
eine Beschleunigung der Dekodierung erreicht werden, indem ein Teilprozess
– die sogenannte Deblocking-Filterung – an eine anwendungsspezifische
integrierte Schaltung delegiert wird.
WS 2006/07
- Rauf Salimi Khaligh
Transaction Simulation of ARM Based Platform
ARM is a family of microprocessors that is widely used in embedded systems.
These systems typically include hardware accelerators, peripheral components,
and memories which are connected with the ARM processor via a bus system,
together forming a so-called platform. In this thesis an efficient simulation
system for such a platform, based on SystemC and Transaction Level Modeling
was developed. The ARM instruction set simulator ("Armulator") has been
integrated into the simulation system. A library of basic models, e.g. for
memories and the AMBA bus system has been developed. The simulation system
has been tested with a sample application.
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