Eine domänenspezifische integrierte Entwicklungsumgebung für Laserscanner-Systemfirmware

FARO Technologies Inc. baut Messmaschinen, die Abbildungen der Umgebung in dreidimensionale Modelle am Computer umsetzen können. Das FZI hat für das Unternehmen die Entwicklung der Systemfirmware für einen der derzeit besten 3D-Laser-Scanner auf dem Markt optimiert. Die Intelligenz der High-Tech-Messgeräte steckt in verteilten, ins Gerät eingebetteten Systemen mit programmierbaren Bausteinen - so genannten FPGAs (Field Programmable Gate Arrays). Die Systemfirmware für solche hoch entwickelten technischen Systeme permanent zu verbessern, um im Spitzenfeld von Markt und Technik zu bleiben, ist eine grosse Herausforderung. Ein technisch guter und gleichzeitig ökonomischer Entwicklungsprozess ist nur mit leistungsstarken Entwurfswerkzeugen realisierbar. Der Forschungsbereich "Embedded Systems and Sensors Engineering" (ESS) am FZI hat im Auftrag von FARO für den Entwurf moderne Technologien und Methoden aus der universitären Forschung auf den Entwicklungsprozess für die Laser Scanner LS Systemfirmware übertragen und Lücken in der bisherigen Werkzeugkette durch proprietäre Tools geschlossen. Das Ergebnis ist die neue Entwicklungsumgebung "Embedded Systems Development Environment" (ESDE) für den durchgängigen domänenspezifischen Entwurf von verteilter und eingebetteter Hardware/Software Systemfirmware auf Basis von rekonfigurierbaren Architekturen.
Die Entwicklungsumgebung ermöglicht einen sogenannten "Meet-in-the-Middle" Entwurfsprozess. Das heißt, der Entwurf für neue Systemfirmware kann in einem Annäherungsverfahren (Iteration) von der abstrakten Modellierung des Systems bis hinunter zur eingebetteten Hardware (Top Down) und in Rückkopplungsschleifen wieder zurück (Bottom Up) immer weiter optimiert werden. Erkenntnisse und Messungen, die bei der Applikation der geplanten Algorithmen auf der Hardware gewonnen werden, können so zum Zweck der Verbesserung beliebig oft in vorherige Phasen des Entwurfsprozesses zurück übertragen werden. Der stufenweisen Optimierung liegen durch dieses Verfahren echte Validierungsdaten zur Grunde.

Selective Hardening in Early Design Steps

Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.

System Reliability Modeling and Reliability Model Evaluation

At system-level hardware-software co-design a designer or system synthesis tool would greatly benefit from a method of early system reliability prediction. Such a prediction would allow the designer or the tool to choose a design alternative which arbitrarily trades off reliability with other system properties of interest.
For reliability modeling, the concepts of fault impact, fault transparency, and fault masking are crucial. Model accuracy depends directly on the the assumptions and simplifications made in these areas. In the early phase of model development its accuracy has to be assessed so that the model could be said to be valid. Furthermore, in order to model reliability of any system, the model has to be given reliability specific information for all its modules. Both problems may be solved using reliability simulation and emulation methods.
In this talk I will present a few contributions to reliability modeling along with introduction to our experimental reliability evaluation approach. Furthermore, I will present our most recent experimental reliability results for a JPEG compressor.

Entwicklung eines Verfahrens zur Temperaturanalyse und -absenkung bei dynamisch rekonfigurierbaren Architekturen

Die steigende Integrationsdichte moderner Halbleiterschaltungen, wie Mikroprozessoren oder Systems-on-Chip (SoC), führt zu einer Erhöhung der Leistungsdichte dieser Schaltungen und damit einhergehend zu einer drastischen Erhöhung der entsprechenden Betriebstemperaturen. Diese Verschärfung des Wärmeproblems begünstigt Fehlverhalten und vorgezogene Alterung oder Zerstörung der Systeme. Bei der Entwicklung komplexer Halbleiterschaltungen ist somit, neben der Senkung des elektrischen Energieumsatzes (Low-Power), die Reduzierung der entstehenden Wärme eine der wichtigsten Aufgaben.
Im Gegensatz zu Mikroprozessoren mit fest angeordneten Funktionseinheiten, ermöglichen es rekonfigurierbare Architekturen durch gezielte räumliche Verlagerung von Berechnungen (Schaltaktivität), den Entstehungsort der Wärme zu variieren. Das Auftreten starker lokaler Erwärmung in bestimmten Bereichen (Hotspots), kann dadurch vermieden werden. In diesem Vortrag wird eine Vorgehensweise für die Temperaturanalyse einer solchen rekonfigurierbaren Architektur vorgestellt, die die Untersuchung verschiedener Verlagerungsstrategien und deren Auswirkung auf die Temperaturentwicklung ermöglicht.

Integrating scan design and soft error correction in low-power applications

In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. In arrays, error correcting coding is the dominant technique to achieve acceptable soft-error rates. For low power applications, often latches are clock gated and have to retain their states during longer periods while miniaturization has led to elevated susceptibility and further increases the need for protection.
This talk presents a fault-tolerant register latch organization that is able to detect single-bit errors while it is clock gated. With small addition, single and multiple errors are detected in the clocked mode, too. The registers can be efficiently integrated similar to the scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.

Hunting Bugs With Tunnel Vision - Finding More by Seeing Less?

In modern chip production, volume diagnosis is essential to increase yield. Rising design complexity and process variations does not allow for simulating silicon behavior or limiting to fault models.
Due to time and memory constraints during high volume test, the failure information available for diagnosis is already very limited today. Our generalization of the SLAT approach considers all available failure information to point out suspect circuit regions.
In current multi site testing and self diagnosis environments it is not only crucial to use as much information as possible to gain the optimal diagnostic resolution. The test response data volume becomes the most critical factor for the test cost and is usually highly compacted.

No Open Seminar talks!

Scan Chain Clustering and a Real Layout: What is the Impact?

Full scan-based design is one of the most popular design-for-test (DFT) techniques that is widely used in very large scale integration (VLSI) circuits or in system-on-chip (SOC) cores. A plenty of extensive research propose scan chain clustering for certain targets including clustering for area and power minimization, clustering for fault diagnosis, etc. Meanwhile, almost all of them consider design only at the high level and do not pay attention on a possible impact of high level constraints on a real layout. In this talk, the influence of several scan chain clustering strategies such as clustering for low power, clustering for fault diagnoses, clustering for low power and fault diagnoses on a real layout is discussed.

Power, Diagnosis, Routing, Compression - Scan Chain Organization Extended

Using multiple scan-chains, the question arises, which scan-flip-flops should be grouped together to form one chain and how flip-flops should be ordered within a chain.
To solve this adequately several application specific issues - besides the routing overhead - have to be taken into account. One of theses issues is the fault-aliasing and fault cancellation which occurs with any of the recent compaction techniques for test responses. Another issue is the power consumption during test application, as the scan cell organization has influence on the switching activity on the one hand and the effectiveness of test planning strategies for low power on the other hand. Furthermore the scan chain organization also affects the effectiveness of compression techniques.
In this talk a comprehensive approach for guiding scan insertion is presented and resulting scan chain organizations for industrial circuits are discussed.

Restrict Encoding

The increasing complexity of digital circuits necessitates the development of new test methods that could maintain low costs of test by offering better efficiencies compared to available solutions. Among available solutions reseeding and test set embedding have been proven very efficient and are widely used in industry to reduce test costs. It has been showed that synergy between these two schemes could be exploited to develop new test methods which posses the potential of coping with future test challenges. The "Restrict Encoding" is such a method which is based on the observation that a large number of test vectors at similar positions in a pattern set are compatible and could be generated using a single fully specified test vector. The idea is to restrict vectors at such positions to a value that covers care bits of all the vectors at those positions and encode the vectors at unrestricted positions with the seed. The restrict information is stored in memory along with the seeds and during test the vectors at restricted positions are shifted into scan chains from memory instead of LFSR outputs. This novel method along with experimental results will be presented in this talk.

Reliability Modeling of Hardware-Software-Systems

Estimating the reliability of hardware-software systems allows to determine the robustness of design alternatives during design exploration. A system model used to derive such a reliability estimate has to incorporate the hardware structure and architecture of the system as well as the performed function. If merely the functional model or the structural model is considered separate from the other one, reliability estimation may be either too optimistic or too conservative.
While an architectural model allows to determine the impact of logical and architectural fault masking on the design's error rate, it fails to correctly predict the failure rate of the overall system. The function that is performed by the design exhibits particular usage and communication patterns that may - depending on the function - result in increased or reduced susceptibility to faults.
We propose a model that combines functional aspects with the architecture of the system. Fault injection and simulation show the optimistic resp. pessimistic nature of simplifying assumptions in published models. The proposed scheme is able to more accurately model hardware-software systems by incorporating functional aspects.