Effincient Pattern Mapping For Deterministic Logic BIST

Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption.The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.

X-Masking During Logic BIST and Its Impact on Defect Coverage

In this presentation a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

Implementing a Scheme for External Deterministic Self-Test

A method for test resource partitioning is introduced which keeps the design-for-test logic on chip test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new compression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range.
The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.

Untersuchung von fehlertoleranten Prozessorarchitekturen

Durch den zukünftig verstärkten Einsatz von Elektronik in sicherheitsrelevanten Anwendungen im Automotive-Bereich wie z.B. Active Front Steering oder Vehicle Dynamics Management (VDM)-Systeme steigen die Anforderungen an die Sicherheit der eingesetzten Hardware. Dies wird z.B. auch in der Europäischen Norm 61508 gefordert. Aufgrund der Fortschritte in der Halbleitertechnologie werden die Strukturbreiten immer kleiner, wodurch wiederum eine höhere Rate von transienten Fehlern zu erwarten ist. Um dennoch mit zukünftigen Systemen die hohen Sicherheitsanforderungen erfüllen zu können, müssen die eingebetteten Prozessoren mit Fehlererkennungsmechanismen ausgestattet werden, die eine sehr hohe Fehlerabdeckung aufweisen. Auf der anderen Seite wiederum sollten die Fehlerentdeckungsmechanismen möglichst kostengünstig implementierbar sein.

In diesem Vortrag werden verschiedene Architekturen (Zweiprozessorsystem, umschaltbares Zweiprozessorsystem und Prozessor mit Eigenfehlererkennung) vorgestellt und auf ihre Fehlerabdeckung untersucht.

Fault emulation

In this presentation a method to accelerate the fault emulation process will be presented.

Fault Simulation for the Signs Gate Netlist Simulator

A large number of commercial tools are available for scientific circuit simulation. However, these tools do not satisfy all requirements on scientific research. Truly scientific measures are difficult to obtain as the algorithms are secret and their correctness cannot be verified.

Product contracts restrict publication and exchange of information and the expenses for software licences are high.

Signs, or SImple Gate Netlist Simulator, is a gate-level circuit analysis and simulation tool for VHDL and ISCAS design descriptions. The topic of this thesis is to extend the software with a concurrent fault simulator to simulate stuck-at-faults on all gate ports in the netlist.

Concurrent fault simulation is based on a general event-driven simulation algorithm which can be applied to arbitrary fault types. It extends an existing true-value simulation on "good-gates" with the simulation of a list of faulty gates, called bad-gates, attached to each good-gate. As Badgates are created for each stuck-at-faults and all good-gates on its fault path, a separate badgate set is created for each stuck-at-fault. During simulation of a test pattern, all badgates not corresponding to an active fault are deleted from the fault list. The remaining bad-gates on the output port represent the stuck-at-faults detected by the current pattern.

Instruction level power optimization for microprocessors

Power consumption is a crucial concern for modern microprocessors. In this talk, techniques that focus on minimizing power consumed by software programs will be presented. The basic idea is to increase correlations among instructions, which might result in fewer signal transitions inside the target processor and hence less power consumption, without causing any semantic variation of the original programs.

Using Hardware Assertions for On-line Validation

As assertions are used during design simulation, they can also be used to monitor the design during operation. Assertions can be synthesized for both automatic verification and for on-line assertion validation. A synthesizable assertion can provide an automatic model that serves as a crosscheck against formal verification. For on-line assertion validation, an assertion can be checked during the lifetime of a design. In this presentation, I will show how assertions can be used in live designs to guarantee that the design works as expected.

Delay Fault Testing in SRAM-Based FPGAs

In this presentation, I propose a test method enabling the delay fault testing in FPGA circuits. This test method can be viewed as a complement approach to those published in the literature. These approaches mainly focus on the delay faults occurring on the configurable interconnect while the proposed method focuses on the delay faults occurring in the configurable logic blocks (LUTs). The test method can be divided in two parts. Firstly, it is defined the requirements for testing delay faults in an isolated LUT. These requirements are obtained from several timing simulations performed on a LUT. From results, it is also developed a particular delay fault model. Secondly, it is presented the test configurations and the test sequence allowing the test of every delay fault in all the LUTs of a given FPGA. As a result, a special architecture has been proposed in which the number of test configurations is equal to that determined in an isolated LUT. This significant result guarantees a minimal test time, very less than that obtained with classical approaches, which are commonly used by the manufacturers. To validate the solution, several logical simulations have been performed in a commercial FPGA: the Virtex from Xilinx. As an extension, a Built-In Self Test architecture has been also proposed and implemented in the Virtex.

Cache - State of the art

In this presentation, an overview over new research aproaches in the field of cache memories is presented. Since the gap between processor speed and the speed of memory increases, there are many interesting proposals to increase the performance of cache.

Low Power Error Detection on High Speed Buses

In this talk I will present error detection mechanisms that allow both high speed buses while still offering low power consumption.

Pseudo-Exhaustive Testing Methods Applied to Diagnosis

Pseudo-exhaustive testing is very attractive in that it can provide full test coverage for combinatorical faults provided that the circuit is designed in a way that this method can be applied. In this talk the basic ideas of pseudo-exhaustive testing will be explained. Some experimental results on wheter it is feasible to apply pseudo-exhaustive test to modern, large circuits will be presented. After that possibilities to extend some of these ideas and algorithms to the field of diagnosis will be presented.

Development of a Generic Gateway for an Event controlled Communication based on a reconfigurable FPGA Architecture with a Softcore Microcontroller

In this master thesis, obeying hardware software co-design methodology, the reference designs for CAN-Ethernet Gateway are developed. The development is based on Altera Nios? Development Kit, Stratix Edition, which includes both hardware and software development platform. The reference designs’ hardware systems with a µC IP core are embedded in the FPGA of Stratix development board, the functions and services of the CAN-Ethernet Gateway are provided by software. And the performances of these reference designs are tested in system and chip level.

Management System of Internet Documents within a Company

The one who possesses information owns the world. This universally acknowledged truth is beyond any doubt with the rulers, managers and, possibly, even with the schoolchildren. The problems of information gathering, collecting and handling emerge at a new and higher quality level. All information received and being developed is fixed in an appropriate way. The material carrier of the fixed information is a document. What is a Document Management System? Current document management technology grows out of the business community where some 80% of corporate information resides in documents. The need for greater efficiencies in handling business documents to gain an edge on the competition has fueled the rapid development of Document Management Systems (DMS) over the last five years. Document management has replaced data management -- the focus of computing for the last twenty years -- as the latest challenge facing information technologists. On this basis I have made an application module needed for the integration in the company’s daily activity of document management. A document retrieval tool integrated into the Windream environment, as requested by the client company. Windream (windows drive enhanced archive management) is one of the most DMS used at present; it is a program for document management and archiving on the basis of the VFS technology.

Investigation Online Testing Technique for DRAMs

We aim to investigate the performance of an online testing circuit of embedded DRAM. The testing circuit will be able to detect the existence of faults without delaying the DRAM performance or even changing its content. The testing technique is mainly based on Enhanced Output Data Compression which can be described in two phases: In the first phase, the content of the fault free memory is compressed and stored in a specific memory area, refereed to as "reference characteristic". This area is updated concurrently with WRITE operations on the DRAM. In the second phase, a new compression of the memory content, referred to as "test characteristic" is calculated and compared with the reference characteristic. This comparison occurs during the periodic refresh operation of the DRAM. The dissimilarity between reference characteristic and test characteristic, if any, would indicate the presence of fault. To validate if the testing circuit is working correctly, we need to simulate two things: First, a running program on the memory which is repeatedly changing its contents, and second, the probable errors which happen to the memory while being online. During this simulation, the response of the testing circuit is monitored to see if it is detecting the faults correctly and quickly. Finally the performance of the testing circuit using this technique is reported.

Implementierung einer externen X-Maskierungslogik für BIST

Bei einem Built-In Self-Test werden die Testausgaben häufig mit einem MISR zu einer Signatur komprimiert. Undefinierte Werte würden diese Signatur invalidieren und müssen daher maskiert werden.

In dieser Arbeit wurde ein Verfahren zur Ansteuerung einer solchen X-Maskierungslogik für BIST entwickelt. Im Gegensatz zu früheren Arbeiten werden die Ansteuerdaten außerhalb des Chips generiert und in komprimierter Form übertragen. Ziel ist es, den Bedarf an zusätzlicher Hardware und insbesondere die Zahl der Übertragungspins gering zu halten.

Power Reduction For Logic Built-In Self Test Using Scan-Chain Disable

To reduce the power of digital high-frequency circuits it is common to use dynamic power reduction techniques such as clock gating. These techniques yield major power savings for the functional mode. However, they are not currently employed to reduce power consumption during test. Therefore, this thesis proposes a method to use clock-gating facilities together with Logic Built-In Self Test (LBIST). In LBIST, except for the first 20% of test time, patterns that detect new faults (effective patterns) are scarce. Often, less than one pattern in a thousand detects a new fault. If such an effective pattern needs only some of the available scan chains to stimulate the detection of the fault, all unnecessary scan chains can be disabled. This work proposes a compute efficient method to statically determine the set of chains that can be disabled. Experimental results are reported for a chip developed by IBM.

Integration eines Dual-Prozessor Boards in ein Controller Area Network

SAPS-RC ist eine Dual-Prozessor-Plattform, die am Institut für Industrielle Informationstechnik, Universität Karlsruhe, entwickelt wurde. Das Basismodul ist mit einem Mikrocontroller und einem digitalen Signalprozessor ausgestattet. Der Vortrag gliedert sich in zwei Teile. Zunächst werden die System-Architektur sowie Teile der System-Software erläutert. Die Kommunikation zwischen Mikrocontroller und digitalem Signalprozessor spielt in diesem System eine wichtige Rolle und wird daher ausführlich dargestellt. Im zweiten Teil wird eine Anwendung aus dem Automobilbereich vorgestellt. Im Zusammenspiel mit anderen Komponenten, die über den CAN-Bus eines Testfahrzeuges miteinander verbunden sind, werden auf dem Dual-Prozessor Board Echtzeit-Modelle zum Erkennen fahrdynamisch kritischer Situationen berechnet.

Entwicklung einer Baugruppe mit seriellen Schnittstellen für gebündelte PCM-Kanäle

In großen Industriebetrieben und Versorgungsunternehmen für Gas, Wasser und Strom sind örtlich weit verteilte Prozesse zu überwachen, zu steuern und zu regeln. Ziel ist dabei die Optimierung der Prozessführung. Für die hierzu nötige Datenübertragung kommen Netze der Fernwirktechnik zum Einsatz, die spezielle Anforderungen an die Fehlersicherheit, die Integration verschiedenartiger Übertragungswege und Protokolle und die effiziente Ausnutzung der Übertragungswege erfüllen müssen. Am Lehrstuhl für Elektrotechnik des Instituts für Technische Informatik der Universität Mannheim werden verschiedenste Übertragungseinrichtungen für Fernwirknetze entwickelt, darunter das Integrated Services Processdata Network (ISPN). In dieser Präsentation wird eine Baugruppe mit seriellen Schnittstellen für das ISPN-System vorgestellt, die im Rahmen einer Diplomarbeit entwickelt wurde.