Eclipse-Based Front-End to Layout Navigation for Precision Diagnosis

Physical defects are assumed to be localized, that is, all the circuit elements like transistors, gates or interconnects affected by a defect are confined to a restricted region in IC layout. By mapping diagnosis results into layout and rapid navigating through the suspected regions of IC layout, the defect mechanism in a faulty chip can be understood more in detail. In this talk, I will present an Eclipse based front-end layout navigation tool, which can handle realistic layout data in GDSII format. Representation of this layout data in Eclipse platform and the data structures to store all layout features will be discussed. Geometrical algorithms will be presented to provide quick signal look-up and design browsing on layout picture. Realization of bidirectional signal localization between layout and gate netlist descriptions will be pointed out.

Partial Scan Design with low-overhead, balanced APTG models

Among the state-of-the-art DFT techniques, partial scan design has been widely accepted as an effective technique to reduce the complexity in sequential circuit testing. In this presentation, I will talk about a graph theoretic method to select a minimal set of flip-flops for scan. First, combinational ATPG is used to generate non-sequential Test Patterns and the fault coverage is compared to the full-scan circuit. After this, the acyclic partial scan circuit is made balanced by duplicating the nodes that exist in different time steps. Combinational ATPG is applied on this combinational representation and the fault coverage is compared with the unbalanced partial scan circuit. For all benchmark circuits investigated, the resulting overhead in the combinatorial model is insignificant.

Implementation of predictive filter on ARM processor for tracking application

The goal of this thesis is to build the tracking system called Inertial Measurement Unit used in an autonomous robotic vehicle or small blimp, the system consists of couple of sensors namely (accelerometers, gyroscope, compass (magnetic field), temperature and pressure sensor), in addition to the microcontroller unit for data processing. The predictive filter used is Kalman Filter. Kalman Filter is a recursive estimator for data fusion, especially in the environment where the measurements are uncertain. In this talk, the Unscented Kalman Filter for the orientation and the Extended Kalman Filter positioning are presented. The approach uses some existing methods to overcome the difficulties in the modelling of the system.

System Reliability Estimation

Ensuring a certain reliability of a mechatronic system becomes more and more important as human life is affected by it. For a careful estimation of the system reliability not only the reliability of the single components have to be taken into account but also the interaction of components. In the hardware domain mapping of functional components to architectural components is an important step in the design flow of complex systems. This step combines information about the single components and their interaction. Recent mapping algorithms are designed to optimize the final system for time, space or power consumption. In this talk we give an overview of methods to estimate and improve reliability from physical up to system level.

A Case Study on Automatic Test Program Generation for Configurable Cores

With the advent of configurable processors, instead of starting from scratch, designers can customize the core by excluding/including pre-defined blocks and specifying appropriate parameters for them. The benefits are short time-to-market and suitability for specific application domains. This work copes with issues regarding automatic test generation to support this new design paradigm, using the Leon2 processor as a case study.

Scan Chain Clustering for Low Power

BIST Power Reduction using Scan-Chain Disable reduced the power by switching off scan-chains not needed for particular faults. The optimization was based on the fault cones and tried to activate only needed scanchains for each and every fault. This was performed on given scan chain configurations which maybe did not take into account the optimization goal of a maximed power saving and thereby splitted fault cones among more than one scanchain. The obtained results can be further improved by reclustering the scan-flipflops into a new scanchain configuration which takes into account the fault cones of the circuit and tries to minimize the amount of affected scanchains.

ADAMA: Adaptive Diagnosis Between Effect-Cause and Cause-Effect

Logic diagnosis is essential during prototyping and to find yield limiters during production. Rising parametric variations in recent process technologies lead more and more to indeterministic failures and reliability problems and the use of traditional static or fault model dependent diagnosis tools is increasingly limited. In this talk, a new statistical diagnosis approach is presented, which locates and identifies arbitrary faults in a circuit, based on its input/output behavior. The method adaptively generates specialized diagnostic patterns to gradually focus on the defective regions of the circuit until the most probable defect mechanisms are derived. The effectiveness and performance of the approach is shown through experiments with benchmark and industrial circuits.

Efficient On-Chip Compaction of Testresponses

Today's VLSI circuits demand for more and more computational power during testing. The constraints of testers memories extort using techniques to compact output responses. Space compactors and time compactors are used in combination to reduce test volume and make testing more cost effective. In this thesis an interest is put into space compactors and their implementation utilizing properties of error-correction-codes. It is known a priori that the degree of their compaction is about one or two orders of magnitude, whereas the capabilities of fault diagnosis are not so obvious. A goal is to determine fault detection and fault diagnostic properties of a set of industrial benchmarks with compactors attached to them. The results are obtained by fault simulation carried out on a software model