Block based statistical timing analysis for fault detectability evaluation

The talk demonstrates the computation of a statistical waveform at every primary output of a circuit to evaluate the detectability of gate delay faults with a given test pattern pair. The basic statistical operations add, sub, min and max over PDFs and CDFs which are represented as a sum of piecewise polynomial functions will first be explained. This knowledge will later be applied to construct a finite state automaton (statistical waveform graph) which represents the probability of a signal being either 0 or 1 at a given time. Finally it is shown how to compute the statistical waveform from every statistical waveform graph associated with a primary output.

Structural In-Field Test and Diagnosis: considerations and challenges

The growing complexity in today's embedded systems makes it increasingly challenging to guarantee a product's fault-free operation during its full life cycle. As a result, periodic in-field test has become increasingly attractive to detect errors and take appropriate corrective measures during chip design and manufacture. In-field test has traditionally been functional in nature and, consequently, may not provide enough insight into the on-chip error behavior to enable fault diagnosis. In this talk, the main issues and challenges for structural test and diagnosis in the field will be discussed and several state-of-the-art on-chip test approaches will be evaluated within this context.

Memory Built-In Self-Repair for the IBM BlueGene Compute Chip

This talk presents a distributed at-speed built-in self test, built-in redundancy analysis and built-in self repair methodology for the processor cores in the IBM BlueGene Compute chips. The scheme tries to reuse as much of the existing test infrastructure as possible. The built-in redundancy analysis logic can compute the repair solutions for all arrays in parallel and requires very low hardware overhead, thus being suitable even for very small arrays. The scheme can be entirely parametrized and supports various array types which are all resizeable.

The ADAMA Software Architecture

ADAMA started off as a proof-of-concept logic diagnosis software written in Java. It currently receives more and more attention from our group because its constituent classes are actually useful also in many other contexts. ADAMA supports parallel pattern fault simulation and diagnosis of arbitrary gate-level faults for quite some time now. Latest developments also enables test encoding and response compaction, cycle-accurate functional simulation of sequential circuits and soft error vulnerability assessment of numerical algorithms. In this talk, I'll give an overview of the concepts behind the architecture and techniques used in ADAMA. The goal is to help (potential) users of the classes in ADAMA as well as to give hints for writing reusable, high-performance Java code.

Parallelized Fault Simulation

This talk will briefly introduce the basics of fault simulation and different ways of parallelization. Parallel architectures of interest may include GPGPUs and the Cell B.E. processor as well as commodity multiprocessor systems. A discussion on benchmark circuits will give insight into the feasibility and achievable speed-up.

Efficient BIST for High Defect Coverage

Defect oriented testing has moved a long way from just an interesting academic topic to a hard industrial reality for high quality demands. As traditional approaches are inadequate in terms of quality and economics to test modern circuits, new efficient schemes are needed.
in this talk, a pseudo-exhaustive mixed mode BIST approach to target high defect coverage will be discussed. All cones up to a given size are tested pseudo-exhaustively, while the defect coverage for the rest of the circuit is improved by using deterministic patterns of fault model dependent approaches (N-Detect, multiple/complex fault models). A new method of pseudo-exhaustive test pattern generation is also discussed. Experimental results show the benefits of this approach in terms of high defect coverage and low required deterministic patterns count.

Infrastructure and Test

Complex systems no longer only consist of functional components as embedded cores or memory blocks. A significant portion of the system is infrastructure required to meet non-functional design objectives. These include yield improvement, debug and diagnosis, effective and efficient test and in recent years fault tolerance. Most infrastructure blocks explicitely target one objective but can be reused to fullfill additional goals from other domains. This talk focuses on two major infrastructure types: Offline test and online fault tolerance.

Test infrastructure is often associated with multiple serial scan (MSS) where sequential elements are clustered into scan chains to increase observability and controllability during test. While increasing testability MSS poses challenges in terms of test time, bandwidth needs and power consumption. Random access scan (RAS) clusters sequential elements into a virtual 2D-memory allowing to read and write each individual element. Thereby RAS designs are economic in test power dissipation, test application time and test data volume, but expensive in area and routing overhead if compared to MSS schemes.

This talk will show the similarity between infrastructure for reliability and infrastructure blocks for offline test. It will be pointed out how online fault tolerance schemes can be reused as compactors during offline test and what benefits can arise from exploiting correlation between test patterns during decompression wrt test application time and bandwidth.

At-speed testing of SoCs / Location aware low power testing

Rapid advance of semi-conductor technologies have made timing defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE Standard1500 are applied to test functionality of each embedded core in SOC but does not verify the corresponding timing specifications. To achieve high delay test quality as well as to accelerate the time-to-market and the time-to-volume, the development of a Plug-and-Play at-speed testing based on a well-defined test interface has become increasingly urgent. A hardware implementation of an embedded delay test framework including the modified test wrapper and the Embedded Delay Test Mechanism is presented to build an entirely embedded delay test environment where at-speed clock is applied inside the chip to increase test accuracy.

Many X-filling methods attempt to decrease the test-induced yield loss due to excessive power consumption by carefully filling the unkonwn bits in scanned Flip-Flops to reduce the total amount of switching activities during test pattern application. However, test-induced IR-drop is not considered in those studies such that some area with congested switching activities is still exposed to the risk of IR-drop causing timing failure or circuit malfunction. Therefore, phyically distribution should be taken into consideration during test pattern generation to obtain more evenly distributed switching activities around the entire chip.

Consideration of Application in Combinational Circuit Reliability Analysis

The soft error rate of combinational logic grows with shrinking feature sizes and rising operation speeds, becoming a major issue in the technologies to come. The existing methods of reliability analysis, however, are too generic to exactly predict reliability properties, as they most often fail to account for design usage patterns. In this talk I will show that for accurate reliability estimation the application has to be taken into account. What is more, I will present a method to significantly reduce the effort of reliability analysis and I will show its accuracy to be satisfying and easily assessable. A Sparc V8 processor executing a few real-world applications will serve as an example showing the influence of application on reliability analysis.

FPGA-to-Host Communication using Gigabit Ethernet

T.B.A.

Built-In Self-Diagnosis for Volume Testing

The advantages of Built-In Self-Test (BIST) are well known, and for embedded memories BIST is already the preferred test method. However, for random logic BIST is less often employed. This is mainly due to the following two reasons: On the one hand, deterministic patterns might be necessary to achieve reasonable fault coverage, yet they are expensive in built-in tests. On the other hand, the diagnostic information provided by BIST-signatures is rather poor. During the last years the first issue has been tackled successfully (e.g. by Abdul-Wahid). This talk deals with the second issue. A new method for Built-In Self-Diagnosis (BISD) is presented. The method's backbone is a combination of extreme space and time compaction, which for the first time allows to store the expected test responses and the failing test responses with negligible overhead on chip. Consequently, all data relevant to diagnosis can be collected during a single self-test session. The BISD method additionally comprises a diagnosis algorithm and a test pattern generation scheme, which overcome aliasing and the reduced diagnostic resolution introduced by the extreme compaction. Experiments with recent, industrial designs demonstrate, that diagnostic resolution is maintaned compared to external testing and the additional hardware needed to implement the BISD-scheme is negligibly small.

Implikationen moderner Many-Core-Architekturen auf die Abbildung von Algorithmen aus dem EDA-CAD-Bereich

T.B.A.

Self-diagnosis in NoC Architectures

Detecting faulty switches in the NoC has been an interesting issue for the researchers in the NoC test area. No matter which parts of a switch are faulty, previous researches have been focused on recognizing faulty switches, omitting them from the architecture and utilize the remained non-faulty switches in the NoC. The objective of this talk is to present a methodology for diagnosing faults inside a faulty switch of a NoC to increase the yield. After manufacturing, using offline test methodologies faulty switches are detected. Then, the proposed diagnosis methodology determines which parts of a switch are faulty and which parts are still working properly. We evaluate the performance of the NoC with semi-faulty switches. Experimental result represents that utilizing semi-faulty switches increases the performance of the NoC.

On-Chip Infrastructure for ATE Emulation

T.B.A.

Title

Abstract

Retargeting a C compiler to the HAPRA/FAPRA architecture

The RISC processor architectures introduced in the undergraduate and graduate lab courses of the institute use a rather simple, nevertheless complete, instruction set. While the programming environment features an excellent assembly simulation and debugging environment, larger software projects would benefit from the availability of a compiler for a high-level language.
The goal of this thesis is to develop an LLVM-based C compiler for the HAPRA/FAPRA architecture and use it to compare the different subsets of the HAPRA/FAPRA instruction set in terms of runtime performance and space efficiency. This talk will focus on the experiences made during the development of the C compiler and the results obtained by using the compiler to generate code for the different subsets of the HAPRA/FAPRA architecture.
The LLVM compiler infrastructure is an open source effort to build a set of reusable components which can be used to build compilers for arbitrary programming languages. LLVM offers an aggressive optimizer which can do both intraprocedural and interprocedural analyses and transformations. It supports static and just-in-time compilation for a wide range of architectures (x86, PowerPC, ARM and many more). LLVM is a mature, production quality compiler infrastructure used commercially by Apple, Cray, Intel, NVIDIA, AMD and others.

SOFTWARE-BASED SELF-TEST FOR SUN'S ULTRASPARC SOC

Testing of digital systems has passed through many different approaches over time; among the most common self testing approaches are built-in self-test (BIST) targeting structural faults, and software-based self-testing (SBST) targeting functional faults.
BIST doesn't need an external tester, and proved good fault coverage, but it requires some design changes which consumes time, money, and power. Furthermore, it places the device under test (DUT) in a non-functional testing mode.
On the other hand, SBST tests a DUT online in the functional mode. But as the complexity of modern microprocessor increases, number of internal states is exploding, and testing them all is impossible.
A promising testing approach that has the advantages of the above two approaches is a software-based self-testing technique that targets structural faults. This approach is based on imposing some constraints on the DUT's interfaces, so that an ATPG tool can be utilized to generate test patterns that can be expressed as functional instructions.
The proposed method is described and applied on the floating-point units of two SUN's UltraSPARC processors which each of them is considered a true system-on-a-chip.

Software-Based Fault Tolerance for Many-Core Architectures

Today's graphics processing units (GPUs) deliver impressively high computational power at very low costs. The latest product generation offers up to 2 TFLOPS for GPGPU applications.
A serious issue of graphics processing units is the lack of hardware-based fault tolerance, due to the fact, that GPUs are designed for fast computer graphics and not for high-performance computing. Within the next years, GPUs will become even more powerful and they will provide extended support for double-precision floating-point arithmetics, but the fault tolerance will remain an open issue.
To ensure reliable results of GPGPU computations, the software has to be aware of faults. Over the years, various schemes and techniques for software-based fault tolerance have been proposed. Algorithm-based fault tolerance is one of these methods. In this talk, an concise overview of different software-based fault tolerance techniques will be given and some of the related problems and challenges will be pointed out.

Fibre Channel over Ethernet

Abstract