Pfaffenwaldring 47
D-70569 Stuttgart
Germany
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Name: | Dipl.-Inf. Stefan Holst |
| Address: | Institut für Technische Informatik Pfaffenwaldring 47 D-70569 Stuttgart Germany | |
| Phone: | +49 711 685 88279 | |
| Fax: | +49 711 685 88288 | |
| Room: | 3.164 | |
| E-Mail: | holst@informatik.uni-stuttgart.de |
Most of the stuff on this site is in English. That is not because I don't like German but I want to avoid maintaining two sites - This single one is hard enough. I hope you don't mind.
There are my major areas of research along with some thesis proposals. All master- diploma- or study-theses I supervise have something to do with these research areas. If you are interested in these areas but none of the thesis topics grabs your attention, contact me anyway. We usually come up with additional interesting topics after short discussion.
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DIADEM: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie Modern manufacturing processes are subject to high variations and a high sensitivity during operation. This project addresses the need for innovative embedded diagnosis solutions for such systems to reduce time-to-market with reasonable costs. |
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Looking for such defects just by microscopy is impossible. Modern chips have 2km (!) wiring squeezed in one cm² and 10 metal layers - and millions of transistors. To analyze the defect with physical probing (microscopy, SEM, etc.), one must have a pretty good idea where the defect is located. This information is provided by logic diagnosis.
During production test, test patterns are applied to the circuit and the response is checked against the expected outcome. If the check fails, the chip did not pass the test and logic diagnosis analyzes the faulty responses to pinpoint possible defect locations.
Understanding defect mechanisms is very important to reach acceptable production yields. For example, if a certain type of defect appears often on different chips, the cause of the defect type can be avoided (through layout or design alterations) to produce a higher number of defect-free chips.
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MAYA: Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität High-end digital circuits need a very large amount of test vectors. Given such high data volumes, test cost is predicted to explode by a factor of 120.This project addresses this challenge by developing and integrating innovative technology for generating and capturing data on-chip. Project Partner: NXP Semiconductors, Hamburg |
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