Name:Dipl.-Inf. Stefan Holst
Address:Institut für Technische Informatik
Pfaffenwaldring 47
D-70569 Stuttgart
Germany
Phone:+49 711 685 88279
Fax:+49 711 685 88288
Room:3.164
E-Mail:holst@informatik.uni-stuttgart.de

Most of the stuff on this site is in English. That is not because I don't like German but I want to avoid maintaining two sites - This single one is hard enough. I hope you don't mind.

Research Topics

There are my major areas of research along with some thesis proposals. All master- diploma- or study-theses I supervise have something to do with these research areas. If you are interested in these areas but none of the thesis topics grabs your attention, contact me anyway. We usually come up with additional interesting topics after short discussion.

DIADEM: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

Modern manufacturing processes are subject to high variations and a high sensitivity during operation. This project addresses the need for innovative embedded diagnosis solutions for such systems to reduce time-to-market with reasonable costs.
The first research topic is logic diagnosis. This is the art of finding possible defects in big circuits just by analyzing the erroneous behaviour. On the left is an example of a defect in a produced chip.

Looking for such defects just by microscopy is impossible. Modern chips have 2km (!) wiring squeezed in one cm² and 10 metal layers - and millions of transistors. To analyze the defect with physical probing (microscopy, SEM, etc.), one must have a pretty good idea where the defect is located. This information is provided by logic diagnosis.

During production test, test patterns are applied to the circuit and the response is checked against the expected outcome. If the check fails, the chip did not pass the test and logic diagnosis analyzes the faulty responses to pinpoint possible defect locations.

Understanding defect mechanisms is very important to reach acceptable production yields. For example, if a certain type of defect appears often on different chips, the cause of the defect type can be avoided (through layout or design alterations) to produce a higher number of defect-free chips.


MAYA:  Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität

High-end digital circuits need a very large amount of test vectors. Given such high data volumes, test cost is predicted to explode by a factor of 120.
This project addresses this challenge by developing and integrating innovative technology for generating and capturing data on-chip.

Project Partner: NXP Semiconductors, Hamburg

My second area of research is test compression. Every produced chip must be tested before it can be sold, but testing half a billion transistors over merely hundreds of IO-pins in a short time is a very challenging task. Moreover to use the very expensive test equipment more efficiently, multiple chips are tested on one machine at the same time. So the fewer pins have to be connected (i.e. the lesser bandwidth is required), the more chips can be tested in parallel. To reduce the test data bandwidth requirements, we are working here on on-chip structured which allow compressed data transfer at very high compression ratios.


Publications

Workshop Contributions

Teaching

SS 2006: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
(Haupt-)Seminar: Designing High Performant Systems: Statistical Timing Analysis and Optimization
WS 2006: Grundlagen der Rechnerarchitektur
SS 2007: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Advanced Processor Architecture
(Haupt-)Seminar: Algorithms for Design-Automation - Mastering Nanoelectronic Systems
Master Thesis: Eclipse Based Frontend to Layout Navigation for Precision Diagnosis
WS 2007: Grundlagen der Rechnerarchitektur
Conception and Implementation of EDA Tools
SoPra: pop2pc
SS 2008: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Hardware-Praktikum
Studienarbeit: Evaluation kommerzieller Werkzeuge zur Diagnose von fehlerhaften Chips
WS 2008: Advanced Processor Architecture
Grundlagen der Rechnerarchitektur
Master Thesis: FPGA Emulation of a GALS Network-on-Chip interconnection
SS 2009: Seminar: Reliable Networks-On-Chip in the Many-Core Era
Hardware-Praktikum
WS 2009: Advanced Processor Architecture
Grundlagen der Rechnerarchitektur
Master Thesis: Software-Based Self-Test for SUN'S UltraSPARC T2 SoC
SS 2010: Hardware-Praktikum
Studienarbeit: Hardware Entwurf eines eingebauten Selbsttests für digitale Schaltnetze
WS 2010: Hardware Verification and Quality Assessment
Studienarbeit: CUDA-accelerated Delay Fault Simulation
SS 2011: Hardware-Praktikum / Rechnerorganisation 2
Advanced Processor Architecture
Grundlagen der Rechnerarchitektur
Internship: High Performance Time Simulation on Parallel Architectures

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