In todays nano-scale manufacturing processes of VLSI chips, small variations are likely to occur during manufacturing. These variations may have serious impact on the timing behaviour of the circuitry and cause delay faults when run at the desired clock speed. While delay faults usually go undetected with standard logic simulation, this will require special e¿ort to simulate, since delay faults are mostly not considered due to increased complexity and performance reasons. Once we can e¿ciently simulate the net-list and extract the timing behaviour of arbitrary faults, the results of the simulation may be used to perform a diagnosis of real faulty chip-responses in order to locate the critical fault sites in the net- list.

Since the delay fault simulation prior to the diagnosis will become quite exhaustive, we will exploit parallelism according to Amdahl¿s Law to increase simulation speed-up by using ¿CUDA-enabled¿ devices for computation. CUDA stands for Compute Uni¿ed Device Architecture, which is a parallel computing architecture developed by the NVIDIA Corporation that utilizes NVIDIA graphics processing units (GPUs) for high-performance computation issues.

The goals of this thesis are the extension of an existing CUDA-based simulation engine to simulate delay faults and its integration into a di- agnosis framework. A series of experiments will serve for validation and performance evaluation purposes.