The growing complexity of today's Systems-on-Chip demands the use of distributed, and sometimes heterogeneous processing elements that communicate with each other using special resources. Currently, the most common communication scheme is a shared bus that spreads across the entire chip and, therefore, poses complex implementation issues as the number of processing elements increases. In order to overcome the inherent limitations of bus-based solutions, the Network-on-Chip paradigm has emerged as a structured way of realizing on-chip interconnections.
The present Master Thesis has its focus on emulating the interconnection matrix behavior of a large Network-on-chip. The main goals of this work are, on the one hand, to enable the rapid characterization of a an on-chip network architecture, and on the other hand, to identify and implement a suitable GALS interconnection strategy on an FPGA.
The network characterization involves the development of RTL blocks to inject and retrieve packets to/from the network as well as a software/hardware mechanism to control the whole emulation process. For these activities the DfX framework will be used to automate the network description as much of as possible.
To implement a GALS network matrix on an FPGA, several techniques are considered: using double flip-flop synchronizers, using mesochronous synchronizers after [1] and using an QDI asynchronous fabric with a custom development flow [2] or with standard development tools [3].
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