Microprocessors are getting faster, smaller, and more complex, thus they are getting more error prone. Also they are widely used and embedded in a variety of systems ranging from small home appliances to airplanes and other critical real time systems, so they need to be reliable, and fault tolerant. Hence, the need for testing is a necessity.

Using conventional external testers for such microprocessors is getting more expensive and complex since the logic and functions of new microprocessors are getting more complex too. In addition, it is inefficient due to some problems that might appear later in the field. Therefore, the idea of self testing has emerged, in which the processor can be used to test itself.

BIST (Built In Self Test) is the main method used nowadays for self testing, in which an embedded hardware test generator and test response analyzer are used to generate and apply test patterns on a chip at the speed of the circuit.

Another self-testing methodology, called Software-Based Self-Testing (SBST), is based on testing a microprocessor using its instructions. Basically, a test program is executed to test the structure of the processor. Both methods run at-speed of the processor, but there are several advantages for SBST over BIST that makes it more preferable:

These challenges and more have been tackled and BIST was improved, but still, the circuit under test must be BIST ready unlike SBST that can target any logic circuit without significant hardware overhead. This research project would focus on the design, application, and evaluation of SBST techniques on a modern microprocessor, the UltraSPARC T2. The goal is to implement an SBST to test the structure of one module within the UltraSPARC T2 and evaluate its efficiency in terms of structural fault coverage.

The T2 provides a good example for developing SBST methods because it integrates all the key functions of a system on a single chip: computing, networking, security, and input/output (I/O), plus tight integration with the Solaris Operating System.