Name: Dipl.-Phys. Rainer Dorsch Address: University of Stuttgart Institute of Computer Science Department of Computer Structures Breitwiesenstr. 20/22 70565 Stuttgart, Germany Room: 0.150 Phone: +49 711 7816 215 Fax: +49 711 7816 288 E-Mail: Rainer.Dorsch@informatik.uni-stuttgart.de

Teaching
- Winter Semester 01/02
  - Computer Organization
- Summer Semester 01
  - Advanced Processor Architecture
  - System-on-a-chip for communication Applications
- Winter Semester 00/01
  - Computer Organization
- Summer Semester 00
  - Advanced Processor Architecture
  - Hardware Aspects of Embedded Systems Engineering
- Winter Semester 99/00
  - Design and Test of Systems-On-A-Chip
  - Parallele Rechnerarchitekturen
- Summer Semester 99
  - Hardware Verification
- Winter Semester 98/99
- Summer Semester 98
  - Synthese selbsttestbarer Systeme
- Winter Semester 97/98
  - Hardwareverifikation und Fehlertoleranz
Conference and Workshop Contributions
- Adapting an SoC to ATE Concurrent Test Capabilities
  Martin Fischer, Ramon Huerta Rivera, Rainer Dorsch, Hans-Joachim Wunderlich
  Accepted at the International Test Conference, Baltimore, October 8-10, 2002.
- RESPIN++ - Deterministic Embedded Test
  Lars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich
  IEEE Proccedings of the European Test Workshop, Corfu, Greece, May 26-29, 2002.
- RESPIN++-Testverfahren für eingebetteten deterministischen Test
  Lars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich
  12th GI/ITG/GMM/IEEE Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Bad Herrenalb, February 24-26, 2002.
- Reusing Scan Chains for Test Pattern Decompression
  Rainer Dorsch, Hans-Joachim Wunderlich
  Journal of Electronic Testing: Theory and Applications (JETTA), April 2002, Issue 2, 241-251.
- Eingebetteter deterministischer Test in Ein-Chip-Systemen
  Rainer Dorsch, Hans-Joachim Wunderlich
  Workshop Functional BIST 00/001 und edacentrum, 19.12.2001, FhG-IIS Dresden.
- Tailoring ATPG for Embedded Testing
  Rainer Dorsch, Hans-Joachim Wunderlich
  Proceedings IEEE International Test Conference, p. 530-537, Baltimore, MD, October 30 – November 1, 2001.
- Reusing Scan Chains for Test Pattern Decompression
  R. Dorsch, H.-J. Wunderlich
  Proceedings of the European Test Workshop (ETW2001), Stockholm, Sweden, May 29 - June 1st, 2001.
- Using Mission Logic for Embedded Testing
  R. Dorsch, H.-J. Wunderlich
  Design Automation Conference (DATE2001), Munich, Germany, March 12-16, 2001, p. 805.
- Rapid Prototyping using the LEON SOC Development Platform. Example: Digital Dictation Machine
  D. Bretz, R. Dorsch, H.-J. Wunderlich
  University Booth of the Design Automation Conference (DATE2001), Munich, Germany, March 12-16, 2001.
- A Modified Clocking Scheme for a Low Power BIST Test Pattern Generator
  P. Girard, L. Guiller, C. Landrault, S. Parvossoudovitch, H.-J. Wunderlich (presented by R. Dorsch)
  2. DFG-Schwerpunktkolloquium "Grundlagen und Verfahren verlustarmer Informationsverarbeitung", TU München, 29. und 30. Januar 2001.
- BIST for Systems-on-a-Chip
  R. Dorsch, H.-J. Wunderlich
  Electronics Design and Test, International User Forum, Tallinn, Estonia, October 11th, 2000.
- Using Mission Logic for Embedded Testing
  R. Dorsch, H.-J. Wunderlich
  1st IEEE International Workshop on Test Resource Partitioning TRP2000, Atlantic City, New Jersey, October 5-6, 2000.
- Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest
  R. Dorsch, H.-J. Wunderlich
  12th GI/ITG/GMM/IEEE Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Grassau, March 19-21, 2000
- Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST
  R. Dorsch, H.-J. Wunderlich
  7th IEEE International Test Synthesis Workshop, Santa Barbara, CA, March 2000
- Accumulator Based Deterministic BIST,
  R. Dorsch, H.-J. Wunderlich
  Proceedings IEEE International Test Conference, Washington, DC, October 1998, 412-421
Supervised Student and Diplom Theses
- Master Thesis: Development of an Audio Player as a SoC - Hardware
  Luis Leonardo Azuara-Gomez
  am 1.1.02 begonnen
- Master Thesis: Development of an Audio Player as a SoC - Software
  Pattara Kiatisevi
  am 1.1.02 begonnen
- Studienarbeit: Deterministische Testmustererzeugung mit eingebetteten Prozessorkernen
  Tobias Bergmann
  am 1.8.01 begonnen
- Master Thesis: Parallel BIST Techniques at Register Transfer Level (RTL)
  Jorge-Luis Sánchez-Ponz
  01.02.2001-31.07.2001
- Master Thesis: SoC Design Guidelines to Perform Concurrent Test of Multiple Cores
  Ramón Huerta Rivera
  19.02.2001-18.8.2001
- Diplomarbeit Nr. 1879: Diagnose und Überwachung von On-Chip-Bussystemen
  Tobias Lohmiller
  01.10.2000 - 31.03.2001
- Diplomarbeit Nr. 1871: Digitales Diktiergerät als System-on-a-Chip mit FPGA-Evaluierungsboard
  Daniel Bretz
  18.09.2000 - 23.02.2001
- Diplomarbeit Nr. 1878: Design, Implementierung und Integration eines Speichertests
  Arno Wacker
  15.08.2000 - 28.02.2001
- Studienarbeit Nr. 1726: Sequentielle Mustergeneratoren für den Test von sequentiellen Cores
  Tobias Lohmiller
  01.02.2000 - 31.07.2000
- Diplomarbeit Nr. 1769: Test von Systems-On-A-Chip mit eingebetteten Prozessoren
  Tobias Schüle
  01.04.1999 - 30.09.1999
- Studienarbeit Nr. 1722: BDDs aus arithmetischen Funktionen
  Jürgen Gross
  16.06.1998 - 16.12.1998
Misc
- My Online Literature Database (always under development). Bibtex file If you find any incorrect entries, please let me know.

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