Name:	Dipl. Ing. Christian Zöllin
	Address:	University of Stuttgart Institute of Computer Architecture and Computer Engineering Pfaffenwaldring 47 D-70569 Stuttgart Germany
	Room:	3.171
	Phone:	(+49) (0)711 / 7816-276
	Fax:	(+49) (0)711 / 7816-288
	E-Mail:	christian.zoellin@informatik.uni-stuttgart.de

Teaching

Exercises

• Elements of High-Performance RISC Processors - Design and Synthesis (WS 2008)
• Rechnerorganisation / Technische Informatik II (WS 2008)
• Elements of High-Performance RISC Processors - Design and Synthesis (SS 2008)
• Rechnerorganisation / Technische Informatik II (WS 2007)
• Hardware-based Fault Tolerance (WS 2007)
• Computer Structure and Organization (SS 2007)
• Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik (SS 2007)
• Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik (SS 2006)

Seminars

• Modern CPU Architectures: Aspects of Parallelism and Energy Efficiency (WS 2006/2007)
• Designing High Performant Systems: Statistical Timing Analysis and Optimization (SS 2006)

Projects

	REALTEST: Test and Reliability of nanoelectronic Systems In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.

IBM CAS Project:  Improved Testing of VLSI Chips with Power Constraints The elevated power dissipation during test has severe impact on test time, test reliability and product reliability, especially for high-performance processors like the Cell Processor. In the course of this project, new methods for test planning that take advantage of clock gating and power gating are developed. Project Partner: IBM Deutschland Entwicklung

Publications

Journals and Conference Proceedings

• Test Exploration and Validation Using Transaction Level Models
  Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
  Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009
• Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung
  M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
  2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Ingolstadt, Germany, 29.09. - 01.10.2008, pp. 107-114
• Integrating Scan Design and Soft Error Correction
  M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
  14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008
• Scan Chain Clustering for Test Power Reduction
  M. Elm, M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, J. Leenstra, N. Maeding
  45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008
• Selective Hardening in Early Design Steps
  C. G. Zoellin, H.-J. Wunderlichm, I. Polian, B. Becker
  13th IEEE European Test Symposium (ETS), Lago Maggiore, Italy, May 25-29, 2008
• Test Set Stripping Limiting the Maximum Number of Specified Bits
  Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich
  4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008 Best paper award
• Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper)
  S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube
  43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), Bled, Slovenia, September 2007
• A Refined Electrical Model for Drift Processes and its Impact on SEU Prediction
  S. Hellebrand, C.G. Zoellin, H.-J. Wunderlich, T. Coym, S. Ludwig, B. Straube
  Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007
  
  
• Programmable Deterministic Built-in Self-test
  A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, F. Hapke, J. Schloeffel, L. Souef
  Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 23 - 25, 2007
  
  
• Scan Test Planning for Power Reduction
  M. E. Imhof, C. G. Zöllin, H.-J. Wunderlich
  44th Design Automation Conference (DAC), San Diego, CA, USA, June 4-8, 2007
  
  
• Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute
  M.E. Imhof, C.G. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
  Tagung Zuverlässigkeit und Entwurf (ZuD 2007), München, Deutschland, 26. - 28. März 2007
  
  
• BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
  C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
  Proc. of the International Test Conference (ITC), Santa Clara, CA, USA, October 24 - 26, 2006
  ftp pdf? (507 KB)
  
  
• Blue Gene/L compute chip: Synthesis, timing, and physical design
  A. A. Bright, R. A. Haring, M. B. Dombrowa, M. Ohmacht, D. Hoenicke, S. Singh, J. A. Marcella, R. F. Lembach, S. M. Douskey, M. R. Ellavsky, C. G. Zoellin, and A. Gara
  IBM Journal of Research and Development, 2005, Vol. 49, No. 2/3, pp. 277-288.
  pdf? (475 K)
  
  

Workshop Contributions

• Integrating Scan Design and Soft Error Correction in Low-Power Applications
  M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
  1st Workshop on Low Power Design Impact on Test and Reliability (LPonTR08), Verbania, Italy, May 25-29, 2008
• Ein verfeinertes elektrisches Modell fuer Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
  Torsten Coym, Sybille Hellebrand, Stefan Ludwig, Bernd Straube, Hans-Joachim Wunderlich, Christian Zoellin
  20th ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen", Wien, Austria, February 24-26, 2008
• Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information
  Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin, Jens Leenstra, Nicolas Maeding
  20th ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen", Wien, Austria, February 24-26, 2008
• Programmable Deterministic Built-in Self-test
  A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, J. Schloeffel, F. Hapke
  ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Erlangen, Germany, March 11-13, 2007
  
  
• BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
  C. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
  ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Titisee, Germany, March 12-14, 2006
  pdf? (8 K)
  
  

Master/Diploma Theses:

Proposals

• Deriving sequential error propagation probabilities from circuit descriptions
• Evaluation of strategies for care-bit reduction in SAT based ATPG

Current

• Fault simulation for complex fault models
• Graphenalgorithmen zur Optimierung von Scanketten im Selbsttest
• Fault analysis for footer devices in circuit designs with power gating
• Software infrastructure for CAD support of complex test architectures

Completed

Other stuff:

• Pictures